Altera, Synopsys plan 'ASIC-like' design solutions for complex PLDs
Altera, Synopsys plan 'ASIC-like' design solutions for complex PLDs
By Semiconductor Business News
November 15, 2001 (5:30 a.m. EST)
URL: http://www.eetimes.com/story/OEG20011114S0051
SAN JOSE -- Altera Corp. and Synopsys Inc. today announced plans to jointly develop ASIC-like design solutions for complex system-on-programmable-chip (SoPC) devices. The partnership will address the need for next-generation design and verification flows for high-density programmable logic devices, said the two companies. The two companies said they plan to leverage standard formats, such as Synopsys' .lib and the Synopsys Design Constraint (SDC) standard, to allow developers to employ ASIC techniques in programmable logic. The overall goal is to improve performance and productivity in high-density PLD designs. An example of an ASIC-like approach to design would be the use of a wide variety of design constraints to control the synthesis process for a desired clock speed and area in PLDs, said Altera and Synopsys. The partnership comes as other design automation suppliers also are attempting to redefine how complex PLDs and field-programmable gate arrays (FPGAs) are used. Mentor Graphics Corp. is now preparing to ship its first beta versions of knowledge-based, heuristic synthesis tools for FPGAs with up to 50 million "ASIC gates." The new synthesis tools are part of an 18-month development effort at Mentor, called the "Atlanta Project" (see Nov. 6 story). Mountain View, Calif.-based Synopsys said it will make available the SDC constraint format, which allows Altera's customers to use the same constraints for PLD designs as used in high-density ASIC synthesis. The same SDC constraints are then applied in place and route, saving time and bringing yet more control to the flow, according to Synopsys. This approach will give designers more control over the final implementation without getting caught in recode-and-reverify loops, said the company. "By leveraging our strength in ASIC design and verification, we provide our mutual customers with the power they need to take f ull advantage of Altera's high-performance programmable logic devices," said Sanjiv Kaul, senior vice president and general manager of the physical synthesis business unit at Synopsys.
Related News
- Off-the-shelf MCU tweaked for ASIC-like duty
- Avnet ASIC Israel Ltd. (AAI) Standardizes on Synopsys' Design Compiler Graphical to Accelerate SoC Design Cycle
- Synopsys' PrimeTime Speeds Timing and Power Closure for Complex SoC and IoT Designs
- Key ASIC Deploys Synopsys' Design Compiler Graphical to Accelerate System-on-Chip Design
- Synopsys' IC Compiler II Enables Toshiba's Tapeout of Complex 40-nm SoC, Proves out Game-Changing Capabilities
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |