SAN JOSE -- Altera Corp. and Synopsys Inc. today announced plans to jointly develop ASIC-like design solutions for complex system-on-programmable-chip (SoPC) devices. The partnership will address the need for next-generation design and verification flows for high-density programmable logic devices, said the two companies.
The two companies said they plan to leverage standard formats, such as Synopsys' .lib and the Synopsys Design Constraint (SDC) standard, to allow developers to employ ASIC techniques in programmable logic. The overall goal is to improve performance and productivity in high-density PLD designs.
An example of an ASIC-like approach to design would be the use of a wide variety of design constraints to control the synthesis process for a desired clock speed and area in PLDs, said Altera and Synopsys.
The partnership comes as other design automation suppliers also are attempting to redefine how complex PLDs and field-programmable gate arrays (FPGAs) are used. Mentor Graphics Corp. is now preparing to ship its first beta versions of knowledge-based, heuristic synthesis tools for FPGAs with up to 50 million "ASIC gates." The new synthesis tools are part of an 18-month development effort at Mentor, called the "Atlanta Project" (see Nov. 6 story).
Mountain View, Calif.-based Synopsys said it will make available the SDC constraint format, which allows Altera's customers to use the same constraints for PLD designs as used in high-density ASIC synthesis. The same SDC constraints are then applied in place and route, saving time and bringing yet more control to the flow, according to Synopsys. This approach will give designers more control over the final implementation without getting caught in recode-and-reverify loops, said the company.
"By leveraging our strength in ASIC design and verification, we provide our mutual customers with the power they need to take f ull advantage of Altera's high-performance programmable logic devices," said Sanjiv Kaul, senior vice president and general manager of the physical synthesis business unit at Synopsys.