Compliant with PCI Express Based Specification 2.0 at maximum speed of 5.0GT/s
Hsinchu, Taiwan, April 21, 2010 -- Faraday Technology Corporation (TAIEX: 3035) today announced the availability of its commercial PCI Express (PCIe) Gen2 endpoint (EP) controller. This new component is fully compliant with the industry standard PCIe Based Specification 2.0 at the maximum speed of 5.0GT/s. Combined with Faraday's silicon proven PCIe Gen2 PHY, the complete solution can be offered to the customers today for seamless connection.
Based on years of experience in developing high-speed serial link IPs, this EP controller leverages Faraday's delicate architecture tailored for high throughput and low latency with the minimum involvement of CPU efforts. These advantages will not sacrifice the power consumption and die size; different levels of power management and competitive gate counts are still kept to optimize the design. Faraday also completes an extensive battery of testing methodologies for the controller, including hardware and software validation tests provided by PCI-SIG, which can further guarantee its compatibility and reliability.
“Giga-level transmission interface is one of Faraday's core competences,” said Steve Wang, Chief Strategy Officer at Faraday. “We have a variety of selection, such as USB, SATA, Ethernet, LVDS and PCIe to fully satisfy our ASIC customers. For PCIe, we have completed PCIe Gen1/Gen2 controller and PHY ranging from 0.18um to 90nm. This new PCIe Gen2 controller extends our target application to 5GT/s areas such as USB 3.0 bridge on the motherboards, add-on cards and dongle market as the early adoption. We expect to see more and more applications embedded with our controllers, and this newly-launched IP will make great contribution to our ASIC business.”
The EP controller supports the 16-bit PIPE as the PHY interface, and the AMBA 2.0 AHB interface is equipped to well connect with the CPU and other peripherals. Besides these flexible features, Faraday offers the PCIe emulation system to customers for their evaluation and development. This emulation system, integrating the controller inside the FPGA with PHY test chip on board, has passed all the testing criteria and been acknowledged in the PCI-SIG Integrators List.
“Our complete PCIe portfolio will be achieved step by step.” said Allen Chen, Associate Vice President at Faraday. “Our next step is to develop the multilane device controller and Root Complex (RC). With the total solution of PHY and controller, we are confident that our PCIe solutions can satisfy all of our customers.”
Faraday's PCIe Gen2 EP controller and the PHY in UMC 90nm (SP) are now available.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading fables ASIC and silicon IP provider. The company's broad silicon IP portfolio includes Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express. With 2009 revenue of US$ 160 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: www.faraday-tech.com