Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
DOLPHIN Integration promotes equivalence checking for multi-level modeling
Grenoble, France, April 30, 2010 -- System-On-Chip (SoC) are becoming more and more complex and their simulation takes ever longer. In order to optimize the tradeoff between accuracy and simulation speed, the appropriate solution is to model the different blocks of the SoC at different abstraction levels. For example, in a mixed-signal SoC, some components can be modeled in SPICE for best accuracy, whereas other components can be modeled in behavioral languages such as Verilog and VHDL, or their analog equivalents Verilog-A and VHDL-AMS. What is at stake with this approach is to ensure that the behavioral model of a component and its structural representation behave equivalently in some sense, either way, thereby enabling the use of behavioral models for blocks within complete SoC simulations.
In addition to its capabilities to simulate mixed-signal and multi-language designs, SMASH allows performing template-based equivalence checking between models at different levels of abstraction, or with respect to a specification or a given standard. The template can be either the written description of the specification/standard or the result of a reference simulation, whereas the profile to compare is either the result of a simulation or the result of some post-processing, such as an FFT or Jitter extraction.
For standard cell and memory designers, thanks to an extended support of vector files (.vec), it is easy to define patterns to apply to logic designs, whether simulated at the logic behavioral or structural levels or at the electrical level in SPICE, as well as the expected output templates. Warning messages enable to quickly identify which signals violate the templates and when.
For analog designers, based on the existing powerful measurement and extraction capabilities of SMASH, the upcoming Spring release will extend equivalence checks for analog and electrical signals.
For more information on equivalence checking, feel free to download the presentation sheet or contact Nathalie Dufayard at solutions@dolphin-integration.com
The free discovery options of SMASH are available for download at: http://www.dolphin.fr/medal/smash/smash_download.php
|
Dolphin Semiconductor Hot IP
Related News
- DOLPHIN Integration promotes a complete offering of detectors for on-the-fly checking
- DOLPHIN Integration promotes Application Hardware Modeling to optimize system functions
- Leading-edge demonstration of Application Hardware Modeling for SoC Integrators and Application Engineers of Fabless suppliers by Dolphin Integration
- Dolphin Integration revolutionizes subsystem performance validation with Application Hardware Modeling
- DOLPHIN Integration is completing its offering of Custom Training Products after a market test in Asia
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |