Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)
The C65C02 improves the original MOS Technology 6502 performance while retaining full instruction set compatibility
Bielsko-Biala/Poland, May 6th, 2010 - The silicon intellectual property (IP) provider, Evatronix SA, today announced the C65C02 – a 65C02 compatible microprocessor IP core that complies with the original 6502 Instruction Set Architecture by MOS Technology. A list of smart improvements makes the core better suited for non-obsolete uses while retaining compatibility with all the industry certified software should the IP be used as a direct 6502 or 65C02 chip replacement.
The most significant feature of the 65C02 architecture is the introduction of two additional instructions for efficient power management – STP for processor halt and WAI for wait for interrupt. These instructions also decrease overall interrupt latency and enable synchronization with external events.
Significant optimization was implemented in opcodes. These were documented, and instructions that can push or pull .X and .Y index registers to/from the stack were introduced. Undefined opcodes were converted into NOPs (No Operation Performed). The 65C02 ISA addresses and fixes numerous problems with system flags, and significantly increases the usefulness of decimal mode.
“We are introducing the C65C02 both to compliment our 8-bit obsolete part replacement IP, like C8051 or CZ80 for Intel 80C51 and Zilog Z80 architectures respectively, but also to meet demand for a low cost, configurable microprocessor that is targeted for low power applications,” said Maciej Pyka, Processors and Platforms Manager at Evatronix. “Our expertise in development of robust IP has been confirmed by testimonials from a European telecommunication giant and a high precision printers manufacturer.”
The Evatronix C65C02 IP core is available for licensing now. The list of deliverables includes synthesis and simulation support scripts for most popular environments, as well as Verilog or VHDL test bench and a reference design for the proprietary evaluation board.
Evatronix SA, founded in 1991, develops electronic virtual components (IP cores) along with complementary software and supporting development environments. The company also provides electronic design services. Product lines cover a multitude of solutions from interface controllers and microprocessors to integrated System-on-Chip development platforms.
Evatronix is a renowned provider of 8051 microcontrollers, SuperSpeed USB 3.0 and USB 2.0 controllers and memory controllers – ONFi 2.2 compatible NAND Flash and SD 3.0/SDIO 2.0 and eMMC 4.4 compatible SDIO Host controller, among others.
Evatronix IP cores are available directly or through the sales network of its strategic distribution partner, CAST, Inc. Evatronix is headquartered in Bielsko-Biala, Poland, and employs over 75 engineers. For more information about the company please visit the company’s web site at www.evatronix-ip.com or contact Jacek Duda at +48 32 231 11 71 ext. 22 or jacek.duda(at)evatronix-ip.com