San Jose, Calif. – May 10, 2010 – Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced PathFinder™, a full-chip electrostatic discharge (ESD) physical integrity solution to address the increasing reliability challenges faced by nanometer designs. It delivers innovative technologies in modeling, extraction, and simulation for ESD verification, targeting early prototyping, circuit optimization and full-chip signoff. PathFinder’s core technologies include:
- native handling of clamp cell snap-back characteristic for dynamic SPICE like simulation
- built-in extraction and handling of large scale power/ground RLC, substrate RC, and package parasitics
- layout based full-chip analysis of ESD events such as Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM)
ESD charging or discharging is a full-chip verification challenge. In addition, ESD clamp cell design and optimization for custom I/O and analog macro requires SPICE like accuracy. PathFinder is a high throughput solution with unique productivity advantages including:
- 100 million+ instances with overnight turnaround time for static ESD verification
- 100’s of thousands of transistors block including clamping devices for SPICE accurate dynamic ESD simulation
- layout-based debugging GUI environment for cross probing and ‘what-if’ analysis
As the process technologies move towards 40nm and below, designers are facing reliability challenges introduced from the use of smaller wire geometries and thinner gate oxides with lower breakdown voltages. In addition, the use of multiple power and ground networks requires the inclusion of ESD protection circuitry inside the core of the chip. The cost associated with an ESD induced failure can be significant, whether from insufficient protection resulting in low product yield, or from excessive or ineffective protection resulting in wasted silicon real estate.
Today, ESD verification is performed manually based on engineering guidelines for layout, plot checking, or design rule (DRC) checks. But these approaches cannot ensure that the overall resistance and current density of the ESD paths is below the threshold limits. As a result, they cannot exhaustively identify devices or wires that may potentially fail during a specific ESD event before tape-out. In addition, it is important to include the discharging paths through the package for full-chip ESD signoff.
Circuit analysis of I/O, analog, and mixed-signal designs is also critical for ESD layout and design optimization. There is no transistor-level dynamic solution available today that can efficiently simulate large-scale macros including the impacts of clamp’s snap-back characteristics, P/G and substrate networks, and package parasitics with SPICE like accuracy and convergence property.
At the full-chip level, PathFinder verifies the placement and connectivity of ESD cells for HBM, MM, and CDM, based on layout information and design rules. It computes the impedance in the discharge path through the distributed power/ground and package mesh and the participating clamp cells. It verifies the effective resistance between a) pads/bumps to other pads/bumps; b) between pads/bumps to clamp circuits; c) between multiple clamp circuits; and d) between active devices and clamp circuits, for pass/fail check. Increasing current flow through the metal layers of the discharging path can also cause electromigration (EM) induced damages to interconnects. PathFinder provides current density check for all power/ground metals, I/O nets, and clamp devices, allowing the designers to verify that the current flow during discharge event is within the established limits.
PathFinder can also simulate transistor-level netlist such as I/Os, PLLs, and Serdes. It incorporates eSIM™, Apache’s proprietary simulator for ESD transient analysis with SPICE level transistor model. eSIM can handle negative resistance in snap-back devices, which typically causes non-convergence and slow down in classic SPICE simulators. In addition, eSIM with its dedicated matrix solver can handle large scale power/ground, substrate, and package mesh networks, including non-linear devices. PathFinder performs stress check across junction voltages of all transistors during the simulation to identify potential device failures due to ESD events such as CDM. To help with debugging and isolating circuit and layout issues resulting from an ESD event, PathFinder provides a GUI environment with overlay of the simulation results on the layout.
“Through close partnership between our R&D and leading customers, Apache continues to demonstrate the ability to deliver innovative solutions that addresses the next generation design challenges,” said Andrew Yang, CEO of Apache. “ESD integrity is clearly an emerging challenge for power and noise area which is Apache’s core competency.”