IP Integration, Reuse and Design Team Communication Enabled by Socrates Platform
DUBLIN-- May 25, 2010--Duolog Technologies, the award-winning developer of IP and SoC integration products, today announced that its Socrates Chip Integration Hub supports key elements of the EDA360 vision recently unveiled by Cadence. EDA360 cites the growing need for an “Open Integration Platform” to improve productivity and profitability through integration of hardware and software development activities, accelerated software development, improved IP integration, IP reuse and open standards. The Socrates Chip Integration Hub is a standards-based IP integration platform that addresses these issues by raising the level of abstraction at which IP is handled, centralizing and synchronizing design and IP metadata and automating many of the steps involved in the creation of virtual prototypes, FPGAs and SoCs.
“We developed Socrates with the aim of providing a comprehensive, yet extensible, platform to standardize, centralize and synchronize IP metadata in order to improve IP creation, validation and integration. The automatically generated design views provide validated and coordinated data to the software, hardware and architecture teams,” said Ray Bulger, CEO at Duolog Technologies.
More information about realizing the EDA360 vision with Socrates is available at:
Socrates Addresses System and SoC Realization
Socrates provides many features to improve the automation and productivity of SoC realization. For example, auto-generation of design views from a central, verified, source ensures that geographically dispersed engineering teams remain synchronized at all times, and that costly bugs due to misalignment, miscommunication or misinterpretation are eradicated. From a single IP metadata description, Socrates can auto-generate multiple views including documentation, virtual models, RTL models, OVM models and bare-metal software headers.
Socrates uses a unique “rules-based” IP assembly technology that eliminates the use of cumbersome and error-prone scripts. A few simple rules can generate thousands of lines of correct-by-construction interconnect in Verilog or VHDL. Equally important, concise rules files can be used to generate SystemC models for virtual prototypes or RTL models for FPGA prototypes in order to facilitate early software development, an important part of system realization.
Socrates is a customer-extensible platform built on the superb Eclipse IDE and supporting the IP-XACT standard as well as many other open formats.
Duolog will be attending the 47th Design Automation Conference in Anaheim, California, from June 14th to 16th (booth #568) where it will be demonstrating how the Socrates Hub improves SoC integration and design team communications.
About Duolog Technologies
Duolog Technologies Ltd. is an award-winning developer of EDA tools that enable the flawless and rapid integration of today’s increasingly complex SoC, ASIC and FPGA designs. Duolog’s Socrates Chip Integration Hub employs a modular and extensible suite of tools for I/O layer definition, IP packaging, SoC connectivity, hierarchy manipulation and register management.