New Data-Sharing Capabilities in ActiveDesign and JasperGold Unify Design and Verification Teams
MOUNTAIN VIEW, Calif. – June 2, 2010 – Jasper Design Automation, provider of advanced formal technology solutions, today announced new versions of ActiveDesign™ and JasperGold® with capabilities that bridge the divide between chip design and verification by sharing a common, persistent knowledge base. Jasper’s ActiveDesign with Behavioral Indexing™ lets users design, concurrently modify, and verify their RTL code, then store it in a persistent database containing both the RTL itself and an “index” of its elastic behaviors. This information is shared downstream with the JasperGold verification team, facilitating increased collaboration between groups. Benefits are unity among multiple design groups and verification teams, a reduction in information demand on designers, acceleration of verification, and increased IP reuse since design behaviors are now archived and easily accessible.
“ActiveDesign with Behavioral Indexing is the core technology that allows RTL developers to store information, building persistent value databases that can later be used by other designers or verification engineers,” said Dr. Rajeev Ranjan, Jasper Chief Technology Officer. “ActiveDesign and JasperGold work synergistically. Designers using ActiveDesign explore blocks, waveforms and their key behaviors, creating and archiving important information. ActiveDesign can then export properties (asserts, assumes, covers, in SVA and PSL) for transfer to other designers or verification teams using JasperGold.”
In addition to the new unified design-to-verification flow, Jasper has added several new capabilities to its tools to increase rapid adoption, high-level verification acceleration, and increased ROI for formal verification users.
ActiveDesign Version 2.0
Version 2.0 of ActiveDesign, named an EDN Hot 100 Product in January, includes the ability to share information with JasperGold as described above, along with several new, automated fast-start and collaboration features.
EasyStart automates the identification of clocks and resets so designers can explore new RTL blocks faster. AutoExplore examines behaviors of interest by displaying contributing causes and paths back through the design to show causality. With concurrent modification, different designers can work on the same code while an intelligent management system prevents overwriting. ActiveDesign’s hierarchical design support lets an RTL block be instantiated repeatedly at different levels in the design to efficiently deal with complexity, and a new parallelization feature distributes ActiveDesign across multiple platforms for increased throughput.
JasperGold/JasperCore™ Version 7.0
The JasperGold Formal Verification System now has 50% higher performance and capacity, aided by new engine technology and modeling abstractions. ProofGrid and new ProofGrid Manager support user-controlled and distributed proof engines to reduce the time needed to reach full proofs. A new management capability accelerates convergence of deep formal proofs, leveraging Jasper’s leading design-space tunneling and promoting both proactive and after-the-fact RTL tree exploration of design complexity. And versatile JasperGold now has enhanced handling of the toughest formal verification tasks such as
X-propagation, multi-cycle path analysis, clock domain crossing (CDC), and certification of the latest protocols such as DFI and AMBA 4 (enabled by designer-friendly Jasper Proof Kits).
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 150 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.