The Open SystemC Initiative (OSCI) aims to create a set of working groups now that the core language has reached version 2.0 and a level of stability as the focus shifts towards how the SystemC language can be used for modelling systems.
As a language, SystemC has been criticised because of the way that it has been seen in some quarters as no more than a replacement for hardware description languages such as Verilog and VHDL.
Mike Bohm, chief scientist for HDL design at Mentor Graphics, which joined OSCI in the last few weeks once some legal issues had been ironed out, told Electronics Times SystemC is in the position to become a systems modelling language. That is, as long as the right modelling styles and language constructs are in place.
"When I looked at the version 1.0 spec, it was more HDL synthesis. In that form, SystemC was limiting what the industry needs to go forward with. We need a higher level, a behavioural level. Version 2.0 is starting to go down that path," said Bohm.
Kevin Kranen, president of OSIC, said: "With the version 2.0 core language, we believe everything you need to model a system down to hardware is in there. There is a general feeling that we want to extend the core language to model software.
"We want to be able to model multiple operating systems in a system environment. We need to be able to model scheduling.
"Scheduling from a software perspective is different to scheduling from a hardware perspective."
Further extensions would be rolled into the core language, probably version 3.0, that is now the focus of one of the new working groups.
"There are other working groups. There are libraries to be built on top of the core language for domain-specific things.
"Cadence and Philips want to add dataflow modelling. Adam Rose of Motorola in the UK is working on verification: how you model the stimulus of systems under test.
"There are some nascent working groups. An analogue group has not got off the ground yet but it is backed by FHT and Infineon."
Analogue extensions to SystemC would mirror the efforts to add mixed-signal modelling to the Verilog and VHDL in their respective AMS extensions.
"There are discussions on an API working group and there is one more for platform-based design," said Kranen.
The API issue in SystemC is complicated by the fact that there are two aspects to an API: one form would control the models, another the core simulator, which forms part of the environment. The remaining group of the first batch tries to address the problem of brining in existing models.
"The IP [intellectual property] integration group is being set up by Jon Connell of ARM. The aim is to look at how you take blocks of IP and make them accessible to a SystemC environment. It will address how you write a bus-functional model or an instruction-set simulator."
Bohm said methodologies to accompany the basic Syste mC language would be vital.
"That's what we did with VHDL and Verilog. Code after code looks identical out there. A lot of that has to do with style and methodology. We're going to be trying things out," said Bohm.
Kranen said the working groups would take on a lot of the methodology work.
"For example, the dataflow group will share ideas on upper design flows, such as how you capture a dataflow," said Kranen.
"The benefit of an open-source environment like SystemC is that lots of people can use it to build models and create methodologies."
As a language, SystemC received a boost on Tuesday (13th November) with the decision by the last holdout against the language among the small community of C-modelling tools suppliers, Forte Design Systems, deciding to join OSCI.
C Level Design, which criticised SystemC as being too slow, has decided to sell its technology to Synopsys, SystemC's main creator.
Although the next major language changes will be in vers ion 3.0, a parallel effort is underway to define fixes and small tweaks in the core language working group.
One remaining piece of organisational work that OSCI now has to do is find out how to co-ordinate the working groups.
"The [OSCI] board is starting to form the cross-co-ordinating body. The steering group will work out how the groups can work together," said Kranen.