Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)
Live, custom image encoding through a set of configurable parameters that reflect the Evatronix JPEG 2000 Encoder capabilities.
Bielsko-Biala/Poland, June 8th, 2010 - The silicon intellectual property (IP) provider, Evatronix SA, announced today the introduction of an online application that demonstrates the capabilities of the company’s JPEG 2000 Encoder IP core. This free demo system is easily accessable through the Evatronix website www.evatronix-ip.com.
The application was designed to enable users to configure it exactly as they are able to do it with the JPEG 2000 IP core. Many configurable parameters can be set for the best reflection of the desired IP configuration. Also, they can be changed in an instant for comparison purposes.
The demo can handle a wide variety of image storage formats for, both lossless and lossy. The user can upload up to 10 images at the same time and encode them all on the fly. All encoded images are downloadable for further processing.
This demo system is based on an OS agnostic Java engine and does not store any data on the user’s PC. The user just runs a Java application in the browser which links to the Evatronix web server. This server connects to a physical evaluation board featuring a Xilinx FPGA and a dedicated RAM for storing the processed image. The FPGA contains the JPEG2000 encoder along with all required peripherals.
“There is no better way to find out how an image encoder fits the application than to try it with real data,” said Marcin Rodzik, JPEG 2000 Encoder developer at Evatronix. “The availability of the demo, its extensive configurability and ease of use will definitely attract all SoC designers that implement JPEG 2000 encoder IP cores in their application.”
The demo is available here .
About the Evatronix JPEG 2000 Encoder
The JPEG2000 encoder is a full hardware implementation of a JPEG 2000 compression codec, based on the ISO/IEC 15444-1 standard.
The encoder enables flexible configuration of compression parameters for a fully customized image compression level. The full hardware implementation of a TIER-1 and TIER-2 EBCOT encoder allows to define up to 32 different arithmetic entropy coding styles, which allows the user to precisely set size and quality of the output bitstream.
Evatronix SA, founded in 1991, develops electronic virtual components (IP cores) along with complementary software and supporting development environments. The company also provides electronic design services. Product lines cover a multitude of solutions from interface controllers and microprocessors to integrated System-on-Chip development platforms.
Evatronix is a renowned provider of 8051 microcontrollers, SuperSpeed USB 3.0 and USB 2.0 controllers and memory controllers – ONFi 2.2 compatible NAND Flash and SD 3.0/SDIO 2.0 and eMMC 4.4 compatible SDIO Host controller, among others. Evatronix IP cores are available directly or through the sales network of its strategic distribution partner, CAST, Inc.
Evatronix is headquartered in Bielsko-Biala, Poland, and employs over 75 engineers.
For more information about the company please visit the company’s web site at www.evatronix-ip.com or contact Jacek Duda at +48 32 231 11 71 ext. 22 or jacek.duda(at)evatronix-ip.com