Paradigm Works Announces SystemVerilog FrameWorks Template Generator Support for UVM
Andover, MA, June 09, 2010 — Paradigm Works, a world-class leader in ASIC and FPGA software and development services, today announced that its SystemVerilog FrameWorks™ Template Generator software now supports UVM (Universal Verification Methodology).
The UVM Template Generator takes user input parameters and automatically creates a functional framework for a UVM-compliant verification environment. The current UVM Template Generator release is compatible with UVM 1.0 EA (Early Adopter).
Visit the Paradigm Works Download Page to customize, create, and download a framework UVM environment.
Visit UVM World for additional information on the UVM or to download the UVM kit.
|
Related News
- Paradigm Works Announces VMM 1.0 enhancements to its SystemVerilog FrameWorks VMM Template Generator software
- SystemVerilog FrameWorks VMM Template Generator Upgraded for VMM 1.1
- Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM
- Paradigm Works Releases UVM 1.x VerificationWorks
- Paradigm Works Releases Free Open Source UVM 1.x VerificationWorks Scoreboard
Breaking News
- Credo at TSMC 2024 North America Technology Symposium
- Cadence Reports First Quarter 2024 Financial Results
- Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
- Faraday Reports First Quarter 2024 Results
- RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
E-mail This Article | Printer-Friendly Page |