Update: Exar Corporation Acquires Altior Inc. to Provide Additional Growth in Data Compression (February 19, 2013)
First intellectual property cores to execute hundreds of thousands of data streams simultaneously; eliminates need for multiple, parallel software-programmable processors in both silicon and system
EATONTOWN, NJ. — June 14, 2010 — CebaTech Inc (www.cebatech.com), an innovative developer of advanced FPGA embedded system solutions, CebaFlex™, has announced the expansion of its CebaRIP library of rapidly tunable silicon intellectual property (IP) cores with new, multi-stream versions of its GZIP compression and GUNZIP decompression IP targeted specifically at data networking applications. The new cores are the first GZIP and GUNZIP IP cores to execute hundreds of thousands of data streams concurrently without performance degradation, in contrast to conventional cores that – at best – execute only a few data steams simultaneously before performance degrades. The new cores eliminate the need for multiple conventional IP cores or multiple, parallel software programmable processors.
“We developed these high throughput multi-stream cores in response to requests from customers who are building next generation data networking equipment that must handle the delivery of significantly more data to more end users than ever before,” said Ramana Jampala, CEO of CebaTech. “They wanted to steer clear of the design complexity and bill of materials (BOM) burden of deploying large numbers of single-stream cores and/or programmable processors. There are simply no other commercially-available GZIP-compliant IP solutions that can do this.”
The new multi-stream IP cores achieve line-rate performance with an order of magnitude improvement in processing latency, and without compromising the compression ratio. They can also be aggregated to achieve even higher throughput. The cores integrate readily into system-on-chip (SoC), ASIC and FPGA designs and into CebaTech’s CebaFlex™ series of FPGA-based subsystem boards, boosting protocol processing performance by offloading the execution of compute-intensive protocols from the system’s central processing units (CPU).
Serving the network
The multi-stream cores offer context switching that saves state information on data packet boundaries, reducing network latency and increasing throughput. Their performance scales linearly with stream count, enabling the network to service an increased load without performance or quality of service degradation.
“Scalability without adding latency or compromising the compression ratio is critical. For example, web servers must accommodate increased traffic without sacrificing the e-commerce transaction rate, and WAN optimization equipment must be able to service an exponentially increasing number of remote clients,” said Joe Rash, CebaTech’s vice president of business development and marketing. “Meeting such technical challenges is the key to servicing the increased number of high-bandwidth connected users while preserving and improving the on-line experience.”
The new cores are targeted at semiconductor and system design companies that deliver data networking solutions for mobile infrastructure, WAN optimization, content delivery management, WEB servers, network firewalls and policy management. Delivered as synthesizable Verilog RTL cores or as part of the CebaFlex FPGA-based acceleration subsystems, their characteristics include:
- GZIP/ZLIB compliant, supporting IETF standards RFC1950, RFC1951, RFC1952
- Single core throughput greater than 4Gbps in a 45nm SoC/ASIC; can be aggregated to achieve speeds of 64Gbps or higher.
- Compression ratios of 3:1 using Canterbury Corpus benchmark file set
- Support static and dynamic Huffman encoding
- Fully synchronous designs
- Configurable internal memory requirements to balance chip resources
- Easily integrates with external SRAM or DRAM for “state information” memory storage
- Available as C or System C models for system level analysis and prototyping
CebaTech Inc (www.cebatech.com) develops hardware acceleration solutions that boost protocol execution performance in embedded systems. The company’s offerings include its CebaFlex series of PCI Express®-enabled, FPGA-based subsystems for plug ‘n’ play insertion into standard chassis; and its CebaRIP family of rapidly tunable silicon intellectual property (IP) cores that accelerate protocol execution in advanced SoC, ASIC and FPGA systems design for network, storage, storage area network (SAN), network-attached storage (NAS), and communication applications. CebaTech’s offerings are supported by turnkey board and IP development services, and leverage in-house high-level synthesis technology that speeds time to market and reduce development costs.