Grenoble, France, July 2, 2010. Last week, Dolphin Integration delivered block-busting upgrades of their schematic editor SLED optimized with their multi-domain simulator SMASH.
SLED 1.6 provides the means for logic and analog designers to easily and graphically assemble multi-level and multi-domain designs. Handling the disciplines of pins has been integrated into the symbol editor in order to deliver straightforward and secure multi-domain schematic editing with built-in multi-language netlisting in SPICE, HDL and HDL-AMS. Discipline handling prepares the extension with automatic design checking to ensure that only compatible pins are interconnected, such as but not limited to, multi-domain designs which mix mechanical and electrical signals, multi-voltage designs mixing 3.3V and 1.8V signals, etc.
A specific highlight has also been focused on enhancing teamwork awareness with the possibility to share configurations of Design Rule Checkers and to automatically detect external modifications in a design.
SMASH 5.15 benefits from major improvements in terms of speed and language compliance, principally for Verilog and Verilog-A descriptions in addition to SPICE.
In conformance with previous announcement, this release offers the capability to perform template-based equivalence checking. Designers can either check that the implementation of an analog block matches its specification, or that a behavioral analog model of a block is equivalent to its implementation. This functionality can also be used for verifying integration rules such as the Jitter characteristics of a PLL, or the SNR of a CODEC.
For more information on the new features, feel free to download the presentation sheets of SLED 1.6 and SMASH 5.15 or contact Nathalie Dufayard at solutions@dolphin-integration.com
The free discovery options are available for download at: http://www.dolphin.fr/eda
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own missing EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control.