IP Cores, Inc. Announces a New Family of Forward Error Correction (FEC) IP Cores for Ethernet Applications.
Palo Alto, California, July 8, 2010 -- IP Cores, Inc. has shipped the first core of its new high-speed forward error correction (FEC) IP core family.
"Our new CEC1 family of IP cores supports the cyclic error correction code (2112,2080)," said Dmitri Varsanofiev, CTO of IP Cores. "This code is undergoing standardization in the IEEE 802.3 Ethernet standardization group; our core is generating interest among implementers of the 10G, 40G, and 100G Ethernet interfaces".
Cyclic codes are linear block error-correcting codes that have convenient algebraic structures for efficient error detection and correction.
IEEE 802.3 standardization body has selected a (2112,2080) cyclic code as one of the forward error correction (FEC) mechanisms in the standard. The FEC code used is a shortened cyclic code (2112, 2080) for error checking and forward error correction. The code encodes 2080 bits of payload (or information symbols) and adds 32 bits of overhead (or parity symbols) for a 2112-bit FEC block. A burst error of up to 11 bits can be corrected. The FEC provides coding gain to increase the link budget and BER performance.
CEC1 Core Family
The CEC1 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the section 74 IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation). The encoder and decoder functions are completely independent and packaged as two sub-cores, CEC1-66/2112E and CEC1-66/2112D respectively.
CEC1 datasheet is available here.
About IP Cores, Inc.
IP Cores is a rapidly growing company in the field of security, error correction, and DSP IP cores. Founded in 2004, the company provides IP cores for communications and storage fields, including AES-based ECB/CBC/OCB/CFB, AES-GCM and AES-XTS cores, flow-through AES/CCM cores with header parsing for IEEE 802.11 (WiFi), 802.16e (WiMAX), 802.15.3 (MBOA), 802.15.4 (Zigbee), public-key accelerators for RSA and elliptic curve cryptography (ECC), cryptographically secure pseudo-random number generators (CS PRNG), secure SHA and MD5 hashes, lossless data compression cores, low-latency fixed and floating-point FFT and IFFT cores, as well as cyclic, Reed-Solomon, BCH and Viterbi decoder cores.