Algotronix announces an XTS-AES IP core for storage applications

July 13, 2010 -- Algotronix Ltd., Edinburgh, UK announces the availability of an XTS-AES core to meet the NIST SP800-38E recommendation published in January 2010 and the IEEE 1619-2007 standard.

The IP core provides encryption for data storage applications and can be configured to exceed the demands of SATA 3.0 and USB 3.0, as well as smaller footprint configurations for less demanding requirements. The low-cost core features a hardware AES encryption solution that provides AES-128 or AES-256 for hard drives or memory sticks.

“As a design services company, we need the lowest cost core with outstanding support from the vendor”, said Dr. Patrick Hung, CEO and founder of CPO Technologies Corporation based in Santa Clara, CA. “Algotronix has optimised the core for the smallest footprint in our SoC design to provide USB 3.0 performance at the lowest total cost of ownership”.

Data storage encryption is based on the XTS mode of AES. The algorithm includes a Tweakable encryption technique to provide confidentiality with no expansion of data size. This ensures that identical data will be stored as different patterns in each sector of the storage medium. The core supports all the popular FPGA families or ASIC technology, and the IP is supplied as source code, allowing customers to select from different modes and parameterise the performance. The core includes a testbench implementing the XTS Verification System used for NIST validation.

About Algotronix

Algotronix is based in the UK and was established in 1998. It has a proprietary range of advanced crypto IP products. The products have been designed into military, gaming and other secure applications around the world.

About CPO Technologies Corporation

CPO Technologies Corporation has been providing quality electronic design services to both large corporations and start-up companies in Silicon Valley since 2000. It specializes in the entire frontend design flow, focusing on architectural specification, micro architectural design, logic design, functional verification, logic synthesis, and formal verification.