MOUNTAIN VIEW, Calif. – July 27, 2010 – Jasper Design Automation, provider of advanced formal technology solutions, today announced the availability of Proof Kits for the DFI (DDR-PHY) specification, an interface protocol between memory controller logic and PHY interfaces that reduces integration costs while enabling performance and data throughput efficiency. Jasper high-performance, high-capacity formal verification provides the most complete solution for dealing with the complex protocols and timing parameters specified by DFI.
Jasper’s DFI Proof Kits are sets of properties, written in SystemVerilog, for verification of standard interface protocols. Each Proof Kit includes a Formal Testplan providing detailed instructions on verifying DFI designs, plus properties for the protocol that the JasperGold® Verification System can prove against designs employing the specification. DFI solutions are widely used for cell phones, high-performance graphics and other memory-intensive applications.
The new DFI Proof Kits are currently available and provided at no additional charge to current licensees of Formal Testplanner. Other Jasper Proof Kits include AMBA 4 with AMBA 4 AXI, AXI-Stream and AXI-Lite interfaces; LPDDR1, LPDDR2, DDR, DDR2 and DDR3 SDRAM; AHB and AHB Lite; APB; Ethernet MDIO; OCP-IP; PCI-Express; and others.
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 150 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.