Jasper DFI Formal Verification Proof Kits Now Available
MOUNTAIN VIEW, Calif. – July 27, 2010 – Jasper Design Automation, provider of advanced formal technology solutions, today announced the availability of Proof Kits for the DFI (DDR-PHY) specification, an interface protocol between memory controller logic and PHY interfaces that reduces integration costs while enabling performance and data throughput efficiency. Jasper high-performance, high-capacity formal verification provides the most complete solution for dealing with the complex protocols and timing parameters specified by DFI.
Jasper’s DFI Proof Kits are sets of properties, written in SystemVerilog, for verification of standard interface protocols. Each Proof Kit includes a Formal Testplan providing detailed instructions on verifying DFI designs, plus properties for the protocol that the JasperGold® Verification System can prove against designs employing the specification. DFI solutions are widely used for cell phones, high-performance graphics and other memory-intensive applications.
Availability
The new DFI Proof Kits are currently available and provided at no additional charge to current licensees of Formal Testplanner. Other Jasper Proof Kits include AMBA 4 with AMBA 4 AXI, AXI-Stream and AXI-Lite interfaces; LPDDR1, LPDDR2, DDR, DDR2 and DDR3 SDRAM; AHB and AHB Lite; APB; Ethernet MDIO; OCP-IP; PCI-Express; and others.
About Jasper Design Automation
Jasper delivers industry-leading EDA software solutions for semiconductor design, verification, and reuse, based on the state-of-the-art formal technology. Customers include worldwide leaders in wireless, consumer, computing, and networking electronics, with over 150 successful chip deployments. Jasper, headquartered in Mountain View, California, is privately held, with offices and distributors in North America, South America, Europe, and Asia. Visit www.jasper-da.com to reduce risks; increase design, verification and reuse productivity; and accelerate time to market.
|
Related News
- Jasper Releases New Formal Verification Proof Kits For LPDDR1, LPDDR2 and DDR3
- Jasper Introduces Intelligent Proof Kits For Faster, More Accurate Verification of SoC Interface Protocols
- Jasper Launches Security Path Verification App - Industry's First Formal Solution for Detecting Security Vulnerabilities in SoC Designs
- Jasper and Duolog Partner to Combine SoC Integration with Formal Verification
- Jasper Makes Formal Verification Power-Aware with a New Low Power App for Verification of SOCs with Multiple Power Domains
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
- Efinix Rolls Out Line of FPGAs to Accelerate and Adapt Automotive Designs and Applications
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |