Break-through in the embedded Memory market with Dolphin Integration's dual port RAMs
Meylan, France – August 6, 2010. Dolphin’s Dual Port memories are embedding the access strip design technique, with a pending patent, resulting in two major innovations:
- The silicon area of Dolphin’s DpRAM is up to 50% denser than traditional DpRAM,
- Dolphin’s DpRAM offers a new functionality to SoC designers: the full asynchronous access.
Dolphin’s Dual Port memories satisfy any cost-conscious designer thanks to their area reduction capabilities:
- 50% denser than traditional dpRAM!
- Routing over instances starts from metal 4
- Free rotation at R0, R90, R180, R270
Dolphin’s Dual Port memories open up to a new System-level functionality:
Read and Write operations can be performed jointly at the same address on both ports, thus allowing a fully asynchronous access.
These Ultra High Density Dual Port memories are first released for the 130 nm technological process with flexibility from 128 bits up to 512 kbits.
Check up by yourself the performances of these DpRAM on your design: http://www.dolphin.fr/flip/ragtime/013/ragtime_013_ram.html
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation and Foundry independence. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components, resilient to noise and drastic for low power-consumption, together with engineering assistance and product evolutions customized to their needs. For more information about Dolphin, visit: www.dolphin.fr/ragtime
|
Dolphin Design Hot IP
CLICK - The universal solution of power gating for the whole SoC
Always-on Voice Activity Detection interfacing with analog microphones
Low-BoM, inductor-based buck switching regulator with high efficiency, full PWM ...
Linear regulator with ultra low quiescent current for retention applications, DE ...
Retention Alternative Regulator, combines high efficiency in normal mode and ult ...
Related News
- Dolphin Integration introduces new Dual Port memory compilers in TSMC 40 nm
- Dolphin Integration announces a break-through in logic design drastically improving performances
- Dolphin Integration highlights an innovative solution to improve drastically the performance of Embedded Flash memories
- Dolphin Integration launches a 65 nm compiler for Dual Port Register Files reaching the highest density
- Dolphin Integration announces breaking density records with the AURA Single Port memory registers (1PRFile) at 65 nm LP
Breaking News
- Attopsemi's I-fuse OTP IP Embedded into Melexis' Sensor ICs In Mass Production
- TSMC November 2019 Revenue Report
- Hex Five Announces General Availability of MultiZone Security for Linux - The First Commercial Enclave for RISC-V processors
- Andes Technology and Deeplite, INC. Join Forces To Deploy Highly Compact Deep Learning Models Into Daily Life
- Global Unichip Corporation Uses Cadence Digital Implementation and Signoff Flow to Deliver Advanced-Node Designs for AI and HPC Applications
Most Popular
- Xilinx Issues Statement in Response to Analog Devices Patent Infringement Lawsuit
- Synopsys Posts Financial Results for Fourth Quarter and Fiscal Year 2019
- Verimatrix Completes Sale of its Silicon IP Business Unit to Rambus
- UltraSoC donates RISC-V trace implementation to enable true open-source development
- Tech Industry Heavyweight Joins SiFive - Manoj Gujral Tapped As SVP & GM of Silicon Business Unit
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |