DOLPHIN Integration unique actor for Application Engineering of Silicon IP
Grenoble, France, August 20, 2010 -- The complexity of Systems-on-Chip tends to obscure their crucial connections to physical peripherals around it. The leader of Silicon IP for High Resolution converters is facing the difficulties of system peripherals for Audio and Measurement, with a new breed of Application Engineers. They address the all-too-often ignored expenses of performance losses due to connections and their Bill-of-Material increases.
The Silicon IP provider is accompanying their customers to ensure a safe and fast integration of high resolution ViCs in their SoC, with innovative support from Field Application Engineers and with new types of deliverables: models, templates… Specific care must be taken when embedding high resolution Analog Front-Ends in a SoC. Indeed, even if the CODEC of an audio application has a SNR of 95 dB, the final performance, once embedded in a SoC and together with its application schematics, can be degraded up to 20 dB due to disturbances on both the power and clock networks. One of the solutions sometimes envisioned is to overestimate the performance of each component in order to guarantee the performance of the final system. Wrong expectation: a spoiled power supply will anyhow degrade the overall SNR whatever the SNR of the codec!
For several years now, Dolphin’s Application Engineers have acquired a deep understanding of critical issues on so called hot spots of designs and mastered the modeling of application schematics to secure them by simulation. A combination of novel Integration Hardware Models (IHM within SoCs) and Application Hardware Models (AHM within PCBs) can rely on the unique multi-level, Logic and mixed signal, simulator SMASH.
Custom Training Packages (CTP) now ensure sufficient transfer of know-how on modeling. SoC design teams are now offered the keys to reduce Time-to-Market and yield by releasing right-on-first-pass products. Furthermore, application engineers of Fabless Suppliers of SoCs can properly support their own customers.
For more information on the training program and the course description, contact the product manager Nathalie Dufayard at solutions@dolphin-integration.com.
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/eda
|
Dolphin Design Hot IP
Related News
- TDK-Micronas renews its trust in Dolphin Integration's RAM and ROM Silicon IPs
- Power Regulation IPs from Dolphin Integration, now Silicon Proven on GLOBALFOUNDRIES 22FDX Technology Platform
- Dolphin Integration breakthrough innovation for TSMC 180 nm BCD Gen 2 process: Up to 30% savings in silicon area with the new SpRAM RHEA
- Save up to 20 % of silicon area with Dolphin Integration's standard cell library SESAME uHD
- Dolphin Integration unveils extremely dense audio CODECs for application processors at 28 nm and 16 nm
Breaking News
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Cadence Announces Most Comprehensive True Hybrid Cloud Solution to Provide Seamless Data Access and Management
- Dolphin Design expands GoAsic partnership to enhance the semiconductor Industry's Supply Chain
- Cadence Collaborates with MemVerge to Increase Resiliency and Cost-Optimization of Long-Running High-Memory EDA Jobs on AWS Spot Instances
- M31 Successfully Validates 5nm IP Solution to Empower Global AI Applications
Most Popular
- U.S. Subsidy for TSMC Has AI Chips, Tech Leadership in Sight
- Cadence Unveils Palladium Z3 and Protium X3 Systems to Usher in a New Era of Accelerated Verification, Software Development and Digital Twins
- Zhuhai Chuangfeixin: OTP IP Based on 90nm CMOS Image Sensor Process Technology Successfully Mass Production
- Silvaco Announces Expanded Partnership with Micron Technology
- OPENEDGES Unveils ENLIGHT Pro: A High-Performance NPU IP Quadrupling its Previous Generation's Performance
E-mail This Article | Printer-Friendly Page |