Beaverton OR., — August 24, 2010 — Open Core Protocol International Partnership (OCP-IP) today announced the availability of a Transaction Generator (TG), which is a transaction level (TL) SystemC simulator for benchmarking network-on-chips (NoCs) used in multiprocessor system-on-chip (SoC) applications. Utilizing this tool makes simulation of larger systems substantially faster and the results obtained at this higher level can be accurately used as an initial estimate in selecting and fine-tuning NoCs.
As SoCs grow larger, selecting and further shaping the appropriate communication network between the processing elements becomes increasingly critical. The TG generates traffic for network-on-chip according to abstract software and hardware models. During simulation the TG measures performance metrics from the application and platform models, and from the traffic routed through network-on-chip. Because this freely available, highly-versatile tool, works on the transaction level, simulation of larger systems is substantially faster than those done at the clock-cycle accurate level.
The tool is freely available to both OCP-IP members and non-members alike through GNU LGPL, and is useful for all system-level designers evaluating various interconnection solutions in a simulation model of a real, complex system. It can also be used to simulate IP blocks before real implementations are available which enables the design of interconnect and implementation of IP blocks and SW for processors to advance in parallel, saving time, resources, and ensuring a faster time-to-market.
“The work on this Transaction Generator by our Network on Chip Working Group enables co-operation and collaboration among both industry and academic researchers, ensuring synergy advantages in the field of NoCs,” said Ian Mackintosh, president and chairman of OCP-IP. “We are extremely proud to host our forum where the world’s most prestigious universities and industry researchers in the field of NoC investigation can come together.”
OCP-IP’s Network on Chip Benchmarking Working Group is considering the feasibility of releasing an enhanced toolset surrounding the TG, including a hardware TG, (a tool similar to the Transaction Generator, but designed for use in FPGA prototypes) and various monitoring solutions that can assist in NoC evaluation.
Institutions interested in joining the work of OCP-IP’s Network on Chip Benchmarking Working Group should contact firstname.lastname@example.org
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Formed in 2001, OCP-IP is a non-profit corporation promoting, supporting and delivering the only openly licensed, core-centric protocol comprehensively fulfilling integration requirements of heterogeneous multicore systems. The Open Core Protocol (OCP) facilitates IP core reusability and reduces design time, risk, and manufacturing costs for all SoC and electronic designs by providing a comprehensive supporting infrastructure. For additional background and membership information, visit www.OCPIP.org.