Meylan, France – September 06, 2010. Dolphin Integration is the only provider to address the dynamic power consumption challenge at the architectural level with the introduction of a complete Panoply of Memories and Standard Cells, which uniquely offer Dual Voltage capability for the 180 nm process.
Dynamic power consumption being proportional to power supply, the natural method to improve the performance of power sensitive designs is to integrate a multiple voltage architecture. Dolphin Integration is the partner for such specific power optimized implementations. Depending on your needs, Dolphin Integration’s standard cell libraries and memories can be delivered with characterizations for 1.8 V, 1.1 V or both voltages.
Customers’ Benchmark results versus alternative solutions demonstrate that this Panoply enables dividing dynamic power consumption by:
- Up to 4 when operating at nominal voltage
- Up to 7 when operating at low voltageThe Ultra Low Power Panoply includes:
- The Pluton architecture for Single Port RAM
- The Mars architecture for Dual Port RAM
- The patented Cassiopeia architecture for Metal programmable ROM
- The ultra high density standard cell library SESAME uHD-BTF DV
More information on the key features and performances of the Ultra Low Power Panoply is available in the brochure:
Check by yourself the performances of the Panoply on your 180 nm design:
• For memories, follow the link below to request access to the online generators
• For Standard Cells, comparing with any other library is now easy through the Sofia Benchmark and the public standard Motu Uta
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/ragtime