Langen, Germany -- September 13, 2010 – Fujitsu Semiconductor Europe announces its second generation 8-bit CHArge-mode Interleaved Sampler (CHAIS) ADC for optical transport designs based on coherent detection. The new generation supports data rates from 55 to 65GSa/s and is based on the same ground-breaking ADC architecture as Fujitsu’s 56GSa/s CHAIS ADC in 65nm. It offers the ultra-fast sampling rates, wideband input, low noise and high resolution required for long-haul links with data rates of 100Gbps and higher over a single wavelength.
Implemented in a high-performance 0.9V 40nm CMOS technology, the 65GSa/s CHAIS ADC surpasses even the low power performance of the first generation and will support higher FEC overheads for longer reach. The fundamentals of the CHAIS architecture allow for scalability to even higher sampling rates for future transport data rates (400Gbps/1Tbps) and power dissipation that scales with smaller process feature size. Typical power dissipation for a single CHAIS ADC channel in 40nm is only 1.2W, down 50% from the power per channel in 65nm.
“Fujitsu is pleased to continue to offer leading-edge ADC performance to system vendors bringing higher transport speeds to core networks”, said Neil Amos, Director of the Communications Business Unit at Fujitsu Semiconductor Europe. “In addition to providing lower power solutions, scaling our ADC technology to smaller process nodes enables greater functionality in the DSP and a roadmap for smaller form factors for optical module designs”.
Fujitsu’s 4-channel CMOS design allows for more efficient integration with coherent receiver digital cores, typically comprising tens of millions of logic gates and a multi-terabit data transfer rate across the interface between core and ADCs. For the design of single-die transceiver SoCs in 40nm, the Fujitsu IP offering includes high speed 11Gbps SerDes, supporting a range of protocols and data rates, and will also include a complementary high speed 55 - 65GSa/s 8-bit DAC.
In addition to a range of IP blocks to support current and future designs for optical transport, Fujitsu brings key expertise in advanced package design, including patented techniques for thermal management and noise isolation. “Integrating high performance, very low jitter analogue IP with a large, high-current spiking DSP requires careful attention to signal routing and isolation of noise-sensitive circuits”, explained Ian Dedic, Chief Engineer of Fujitsu’s Communications Business Unit. “Fujitsu’s experience in tackling many of the issues facing system and module developers for this type of complex SoC helps to solve real-world deployment issues”.
Fujitsu Semiconductor Europe will be demonstrating the 65GSa/s CHAIS performance at the European Conference on Optical Communications (ECOC) in Turin, Italy later this month. As with the previous generation CHAIS ADC technology, a development kit for the 65GSa/s ADC will be available in January 2011 for customers to evaluate their modulation and FEC algorithm performance using silicon based on field-proven architectures.