Dual Port Register File Compiler (1 Read-Only Port, 1 Write-Only Port)
KaiSemi offers FPGA-to-ASIC replacement with a *Zero NRE* model
Clive Maxfield, EETimes
9/15/2010 11:57 AM EDT
Using what they describe as "a breakthrough in automated FPGA-to-ASIC conversion," fabless semiconductor company KaiSemi say that they can provide customers with a seamless, full turnkey FPGA-to-ASIC solution and sell fully compatible replacement chips at a fraction of the price.
I had a long chat with KaiSemi CEO Gal Gilat earlier this week, and I must say that I was very impressed with what he told me. Today's announcement is focused on introducing KaiSemi to the world at large (they are already well-known in Israel) – in future articles we will consider the KaiSemi flow in much more detail.
For the moment, we need only note that KaiSemi's proven process uses a unique in-house tool, which performs an automated conversion directly from the original FPGA netlist into a functionally-identical ASIC gate-level netlist. This is a key point – they don’t touch the RTL for the FPGA – instead they take the final ("golden") fully-functional FPGA netlist and work from that. In addition to the programmable logic itself, conversion process also includes all hard IP blocks in the FPGA, such as DSP cores, RAM blocks, PLLs, Clock Managers, and external interfaces (DDR, PCIe, etc.).
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