NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
CLK Design Automation announces breakthrough acceleration for AOCV table generation
Amber Path FX SBOCV is now millions of times faster than Monte Carlo SPICE
LITTLETON, MA — September 20, 2010— CLK Design Automation Inc today announced breakthrough performance improvements in stage-based advanced on chip variation (AOCV) table generation with Amber Path FX. Amber Path FX SBOCV generates a full set of AOCV tables for a complete 882 cell TSMC 40 nm library in under 16 hours. Creating the same tables using Monte Carlo SPICE or Fast SPICE would have taken months or even years.
“Amber Path FX is the only practical solution for creating AOCV tables for a full library," said Isadore Katz, President and CEO of CLK Design Automation. "With our table generation solution organizations can finally begin to adopt AOCV, save hundreds of SPICE licenses, and respond to library changes in a matter of hours."
Amber Path FX was developed together with TSMC as part of a collaborative relationship that has been ongoing since 2007. TSMC has validated Amber Path FX across hundreds of test cases and timing paths. Amber Path FX SBOCV table generation is the only qualified table generation solution in TSMC's Reference Flow 11 announced earlier this year.
The latest release of Amber Path FX SBOCV introduces a 100x speedup. Amber Path FX SBOCV uses core technology from CLK Design Automation's statistical variance analysis engine – the same engine used to do transistor level critical path analysis. Amber Path FX is multi-threaded. Performance scales with the number of available CPUs.
About Stage-based On Chip Variation
Stage-based on chip variation is currently being used as a methodology to reduce pessimism during static timing analysis. AOCV derating tables can be used by a variety of STA tools including Synopsys' PrimeTime™ and Cadence Encounter Timing System™. Amber Path FX generates derating tables using cell depth, complexity, and weighting factors as well as design specific statistical information included in the cell library SPICE models.
SPICE based approaches to table generation are constrained by the complexity and cost of modeling statistical variation using Monte Carlo analysis. For example, creating tables for 38 buffers and inverters took 3 weeks with 120 commercial SPICE licenses. A single complex cell in the same library can have hundreds of arcs (versus 2 for a buffer) and take thousands of hours to simulate all of the combinations necessary to generate its AOCV table.
Using a Fast SPICE tool and “smart” sampling techniques could improve the run time but not by enough to make Monte Carlo practical for more than a handful of cells.
Amber Path FX generated tables for all of the combinatorial cells, including all of the complex cells, for all 4 corners of the same 40 nm library including statistical variation using 15 licenses in just 16 hours.
About Amber Path FX
Amber Path FX leverages patented technology to deliver accurate, fast, and practical solutions for high accuracy critical path timing. Amber Path FX uses transistor level statistical static timing analysis (TSSTA) to achieve near SPICE accuracy for both delay and variance. Amber Path FX path analysis is 100,000x faster than Monte Carlo SPICE. Amber Path FX uses industry standard input and output formats to complement existing STA flows.
About CLK Design Automation
CLK Design Automation is the technology leader in high accuracy timing solutions for nanometer semiconductor designs. CLK DA was founded in 2004, and is backed by Morgenthaler Venture Partners and Atlas Ventures. Its Board of Directors includes Barry Fidelman from Atlas, Bob Pavey and Paul Levine from Morgenthaler, and noted EDA entrepreneur and visionary Jim Hogan.
Related News
- FortifyIQ Introduces FortiPKA-RISC-V: A Breakthrough in Public Key Cryptography Acceleration
- Codasip Releases Studio 8, a Breakthrough in RISC-V Automation, and the Bk7 RISC-V Processor Core for Real-Time Computing Applications
- Vivado Design Suite 2014.1 Increases Productivity with Automation of UltraFast Design Methodology and OpenCL Hardware Acceleration
- Mentor Graphics Delivers Breakthrough in Verification Intelligence
- Tensilica Announces Major IC Design Automation Breakthrough, The Automatic Generation of Optimized Programmable RTL Engines from Standard C Code
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |