64-bit processor cores knock at embedded's door
64-bit processor cores knock at embedded's door
By Anthony Cataldo, EE Times
February 25, 2002 (4:01 p.m. EST)
SAN MATEO, Calif. A handful of prominent vendors are about to heave 64-bit microprocessor cores into the embedded-systems market. Though SuperH, MIPS Technologies and Toshiba would like nothing more than to see embedded designers break out of their 32-bit shackles, it's unclear how many designers are ready to take the leap.
Armed with processing engines that could have once gone into servers and workstations, the 64-bit proponents say they can overcome the issues of power and die size while delivering performance long considered out of reach for embedded design.
"A common misconception is that a higher-performance core is not a good solution, because it has higher power and higher cost," said Keith Diefendorff, vice president of product strategy at MIPS Technologies Inc., the first to roll 64-bit processor cores for the embedded arena.
The company is now steeped in the development of its Amethyst 64-bit processor and has signed o n Toshiba Corp. as a development partner. Toshiba expects to launch a product built around Amethyst early next year.
But the MIPS camp is no longer the lone voice preaching the benefits of 64-bit processing. This week, SuperH Inc., the 2001 joint venture between Hitachi Ltd. and STMicroelectronics, will take the wraps off its long-awaited SH-5 processor. The design stems from a partnership between Hitachi and ST that dates back to 1997.
One underlying assumption for these chip vendors is that system-on-chip (SoC) devices are physically ready to absorb 64-bit CPUs without endangering wafer yields. Advanced process technology appears to be a prerequisite. SuperH is making its core available for 0.13-micron design rules; Toshiba is waiting to port its Amethyst-based TX99 to even more advanced 0.1-micron rules.
"I don't think the silicon size for 64 bits is that much larger than for 32 bits that it will cause an issue," said David Aaron Pelavin, director of sales and marketing for SuperH (San Jose, Calif.).
To sweeten their offers of processing power unattainable by any 32-bit core, vendors are building up the infrastructure to help customers overcome the complexities of SoC design. The pros and cons are likely to provoke lively debate at the Embedded Systems Conference the week of March 12.
Some 64-bit architectures being discussed, such as those from MIPS and the new SH-5 core, are built to honor 32-bit legacy code. The SH-5 even goes a step further by being compatible with legacy 16-bit code.
But the 64-bit trailblazers are up against an army of more conservative 32-bit stalwarts. ARM Ltd., for one, maintains that getting embedded designers to embrace 64-bit addressing is a stretch especially when a number of architectural innovations could forestall the move.
John Rayfield, director of R&D for ARM (Cambridge, U.K.), said a few markets, such as RAID controllers, need 64-bit addressing but that otherwise, 32-bit is still the best way to meet design constraints especially when it comes to power.
"For SoC [devices] today the cost of 64-bit doesn't justify it at the moment. And cost from our point of view is power consumption," Rayfield said. He called 64-bit "overkill today and overkill in the medium term."
SuperH says there are ways around power consumption issues. The SH-5, for example, has "clock-gearing" functions to throttle clock frequencies. "There's a frequency divider to decrease the speed of the bus, CPU or peripheral clocks. You can also shut down individual peripherals when you're not using them," Pelavin said.
But ARM's Rayfield said there are limits to widening data paths as an alternative to higher clock frequencies. "When there's so much parallelism the normal laws of diminishing returns start to come in," he said. "At first, you get a little bit more in and then you have to add huge amounts o f complexity to get the next little bit. Meanwhile the power consumption goes through the roof."
The 32-bit CPU vendors are working to identify architectural hot spots that could benefit from wider paths, sparingly used. "From ARM10 onwards, you'll see 64-bit paths from the caches to the core, and from the caches to the outside memory," said Rayfield. "We're adding 64-bit busing where it's appropriate."
Companies like SuperH, MIPS and Toshiba see tangible benefits to wider addressing. A key feature of the SH-5, for example, is its DSP-like single-instruction, multiple-data (SIMD) engine, which accelerates multimedia instructions by packing 64-bit arithmetic code into the processor registers. An application can retain its 32-bit addressing for most of the code and assign multimedia instructions to the SIMD engine, Pelavin said, to accelerate, say, MPEG video. "There are going to be some applications where 64-bit is critical, particularly multimedia," said Markus Levy, senior analyst at MicroDesign Resources.
Even battery-operated systems are not out of reach. Pelavin said the SH-5 could be used as an applications coprocessor in a third-generation mobile phone to run video. MIPS sees 64-bit cores delivering enough horsepower to enable more "soft" functions in wireless apps. "For example, you can use channeling algorithms to reduce the signal-to-noise ratio and lower the cost," MIPS' Diefendorff said.
Still, the 64-bit camp faces an uphill climb. Embedded systems typically trail the performance of desktop systems, which are firmly grounded in 32-bit processing. So too are most SoC designs. "Most of the work we've been doing is around comms systems, where 32-bit is what you need," said Jim Douglas, vice president of worldwide marketing for design house Tality Inc. (San Jose).
Yet proponents of 64-bit processors in the embedded space say they have reason to be encouraged. MIPS, for one, says it has seen a fivefold increase in 64-bit processor licensing deal s since January of last year.
"There is a certain amount of evangelism that needs to happen, but there's also a lot of previously done work along that line," Pelavin of SuperH said.
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