Update: Cadence Completes Acquisition of Evatronix IP Business (Jun 13, 2013)
More configuration capabilities and higher performance for better application fit; greater bandwidth for smoother demo operation. Bielsko-Biala/Poland, September 30th, 2010 - The silicon intellectual property (IP) provider, Evatronix SA, announced today its JPEG2000 Video Encoder IP core has been enhanced with two more configurable options and a set of architecture optimizations for yet better performance and fit into customer application. As of now, the JPEG 2000 Video Encoder features more than a dozen user configurable parameters and processes HD video at 30 frames per second. Also, the company has increased the bandwidth of it’s web servers in response to high interest in the JPEG2000 Encoder demo application available here.
The latest release of the JPEG2000 Encoder IP core has been enhanced with a configurable color depth parameter, which broadened the available 8-bit scale with 10-bit and 12-bit options. The added value for this is the ability to smoothly accept and process various input signal sources of both still and motion pictures. The feature is crucial in applications that work with data incoming in different formats, i.e. medical or aerospace applications.
The Evatronix JPEG 2000 Video Encoder now implements three other image component sub-sampling schemes. Along with the basic 4:4:4 mode, the encoder supports also 4:2:2 (both Vertical and Horizontal) as well as 4:2:0 modes . Moreover, the sub-sampling module features on-the-fly change of the scheme from the basic to the 4:2:2 or 4:2:0 modes.
Additional improvements in the architecture of the JPEG 2000 Encoder and in the external memory organization significantly raised the achievable frequency of the encoder’s pixel clock, and therefore the frame rate.
„These customer-driven modifications and architecture tweaks enable the encoder to support virtually any data input format , be it still image or motion video,” said Adam Bitniok, JPEG 2000 Development Engineer at Evatronix. “The increased performance rate now even meets the high-end market expectations for HD video processing.”
The JPEG 2000 Video Encoder IP Core will be available for implementations in all ASIC and FPGA technologies by mid October. The deliverables will include the RTL source code, support for synthesis and simulation tools of leading manufacturers as well as an extensive HDL test bench. Interested parties are invited to check the online demo here