DOVER, NH-- November 1, 2010 - Intellitech announced today a free version of its NEBULA software to enable FPGA and SoC designers to develop and validate JTAG/IJTAG based infrastructure IP. The software is targeted for designers who want to validate internal JTAG accessible IP blocks and instruments using the PDL language of upcoming 1149.1-2011 and future IEEE P1687. PDL - Procedure Definition Language is common to both standards and enables developers to describe the operation of the JTAG accessible IP. End customers and integrators can then re-use the PDL provided without re-targeting when the IP is integrated into IC level internal JTAG chains. NEBULA version 6.1 is available for free download after registration at the following link http://www.intellitech.com/ijag. Registrations for the software will close after five hundred registrants.
NEBULA supports early versions of the proposed IEEE 1149.1-2011 internal IJTAG test data register definitions and mnemonics and PDL. Spreadsheet views give the user easy access to read and write internal JTAG registers using data values or mnemonic words thus removing the need to count register bits. The software also includes the TCL/TK scripting language for creating robust user-defined and freely deployable instrument and IP GUIs.
NEBULA communicates to the SoC or FPGA via two freely downloadable software packages, ISIS for VCS and iCableserverX for Xilinx USB JTAG cables. ISIS, Intellitech's Simulation Interface Server runs on 64-bit Linux and communicates with VCS to drive JTAG in simulation. SoC developers can record ATE vectors from PDL and TCL scripts running on NEBULA while it communicates over ISIS to the simulation. The software is limited to three devices in the JTAG chain which is suitable for SoCs, and evaluation boards from Digilent, Xilinx, Altera, Hi-tech Global and others. This limitation can be overcome using Intellitech's JTAG IP or JTAG devices in the target design.