Dolphin Integration announces a thrilling release of the already celebrated Cassiopeia architecture for ROM
Meylan, France – November 19, 2010. The latest release of the single metal via-programmable sROMet Cassiopeia is now available as a complement of Dolphin’s High Density and Low Power Panoply of silicon IP for the 130 nm process.
“To maintain or increase their strength on the market, manufacturers of high density consumer and nomadic devices must regularly offer more features to their end customers - while maintaining competitive pricing. Finding the best compromise between low power and cost reduction is a significant challenge for SoC designers”, said Elsa BERNARD-MOULIN, Product Manager, Dolphin Integration Library Product Line.
The Cassiopeia architecture for ROM meets the most demanding power budgets thanks to its smart low power design. Cassiopeia also allows cost reduction thanks to its high density architecture and Design for Yield.
Customers’ Benchmarks demonstrate that the sROMet Cassiopeia is:
- Up to 50% less power consuming and
- 5% up to 30% denser than alternative solutions
Please follow the link below to get access to the key benefits and features of this product:
http://www.design-reuse.com/sip/view.php?id=15733
For more information about the High Density and Low Power Panoply:
http://www.design-reuse.com/sip/view.php?id=23771
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/ragtime
|
Dolphin Semiconductor Hot IP
Related News
- Dolphin Integration complements its 130 nm catalog with a low voltage release of the ROM Cassiopeia
- Dolphin Integration complements their portfolio of ROM with a shrinked variant of Cassiopeia for the 152 nm process
- TDK-Micronas renews its trust in Dolphin Integration's RAM and ROM Silicon IPs
- Dolphin Integration announces a new release of its innovative IDE for the RISC-V ecosystem
- Dolphin Integration augments the TSMC IP Ecosystem at 40 nm ULP eFlash with new TITAN Read Only Memory
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |