MPEG-2 decoder cores facilitate interactive multi-channel streaming for media servers and personal digital video
Amphion extends multimedia IP cores range for MPEG-2 Video Decode with MP@ML and 4:2:2P@ML products for dual/quad-channel multi-stream and demultiplex in SoC/ASIC
Belfast, N. Ireland & San Jose, California (Feb 7, 2002) - Amphion Semiconductor Ltd., the leading provider of semiconductor intellectual-property for multimedia, data security, wireless and broadband communications, today announces the availability of MPEG-2 transport stream demultiplexing and multi-stream decoders for next-generation digital video ASIC and SoC integrated circuits.
The new CS6804 Multi-source MPEG-2 Demux can simultaneously handle 4 transport stream inputs from independent sources, with up to 4 video and 4 audio packetised elementary streams (PES) per input source. The new CS6652 and CS6654 MPEG-2 Video Decoders perform simultaneous decoding of up to 2 or 4 video elementary streams (ISO/IEC 13818-2 compliant), supporting both MP@ML and 4:2:2P@ML. The decoders can be configured to handle a single elementary stream at 4:2:2P@HL, and optional "lite" versions are available that decode and store only essential parameters from the MPEG-2 video stream. This remarkable architectural flexibility enables designers to create a broad range of high-speed video applications for emerging high growth markets.
"Core-based system-level integration is vital if video chip designers want to create cost-effective systems that combine all the hot interactive multimedia features wooing consumers. Four streams of 4:2:2@ML definition video in a small area, low power core is hard to beat," observed Stephen Farson, Amphion"s VP Engineering. "The decoders have a fully integrated memory system that doesn"t require host processor intervention to run. Digital video designers can drop them into a chip design with little, if any, modification and have a fully functioning multistream MPEG2 video decoder."
Delivering MPEG-4 over MPEG-2
MPEG-2 transport streams can deliver MPEG-4 ("mp4") content - the two standards were designed to be compatible. Also, MPEG-2 content can be included in an MPEG-4 scene description. Combining MPEG-4 with MPEG-2 enables an appealing level of personalization and interactivity for digital TV broadcasts, multimedia entertainment systems, and advertising. The CS6552 and CS6554 cores can be particularly useful for next-generation Picture-in-Picture (PiP) systems where MPEG-2 content will be common in the MPEG-4 composite. For instance, an enhanced digital set-top box (D-STB) can be designed using Amphion"s CS6804 transport demux, CS6552 Dual-stream MPEG-2 Video Decoder, and CS6750 Ultra-low-power MPEG-4 Video Decoder cores.
High Performance for Digital Video applications
The CS6804 transport demux can achieve a maximum throughput of 800 Mpbs with single channel input rates up to 300 Mbps. The CS6652 and CS6654 decoders can process 300 Mbps to cover even the most demanding high definition video applications such as:
* Multi-feature digital set-top boxes offering, for example, "record chatshow while watching news, weather, soap channel in other rooms"
* Picture-in-Picture (PiP) viewing of 1, 2, or 3 alternative camera angles (sports coverage)
* DVD Home Theater systems - standard- and high-definition
* Media servers
* Personal Video Recorders (PVRs)
* Video conferencing
* Multi-point surveillance
In TSMC 130nm ASIC technology the CS6554 requires 106K logic gates, and 900 milliwatts (worst case) when clocked at 133MHz. A comparable DSP-based solution would require four DSPs running at 600 MHz and consuming in excess of 200 watts.
"An increasing number of designers are beginning to realize that highly parallel architectures in fixed-function cores are the most efficient approach for handling compute-intensive, repetitive tasks such as video decoding," explained John McCanny, Amphion CTO. "Off-loading video from the DSP or general purpose processor lets the designer build a more exciting application while spending fewer resources."
These intellectual-property cores are available for license now. OEMs and systems designers interested in Amphion MPEG-2 cores for SoC/ASIC projects can contact Amphion directly. Amphion is an MPEG LA® MPEG-2 patent portfolio licensee.
Amphion is the leading supplier of application-specific cores for IP-based System-on-a-Chip (SoC) integrated circuit designs for multimedia, data security, wireless and broadband communications. Amphion delivers high-performance solutions for video and image compression, advanced encryption, and speech and channel coding with a comprehensive range of silicon- optimized products. Using proprietary techniques for the direct-mapping of processing functions and algorithms into hardware, Amphion develops and licenses semiconductor intellectual-property (SIP) cores that are close to optimal in terms of power, cycles, and area - typically 1 to 3 orders of magnitude better than competing solutions. Amphion cores operate standalone, or by direct interface to industry-standard RISC and DSP processors, and can be easily migrated through different generations of fabrication technology, thus preserving engineering investments in SoC design. Amphion is a privately held company with corporate headquarters and engineering in Belfast, Northern Ireland, UK and worldwide sales and marketing headquarters in San Jose, California, USA. Amphion was formerly known as Integrated Silicon Systems Ltd, or ISS. For more information, visit http://www.amphion.com
Notes to Editors
Amphion, The Amphion logo, and "Virtual Components for the Converging World" are trademarks of Amphion Semiconductor Ltd. All other brand names or product names are trademarks or registered trademarks of their respective owners.
David Mann, Amphion
Europe/Japan: +44 (0) 28 9050-4040
Ron Sailors, Amphion
North America: (408) 441-1248