Avery Design Systems Synthesizes Microarchitecture-Level Assertions and Coverage Properties

ANDOVER, Mass.--January 24, 2011 --Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced it has developed a new capability for Insight formal analysis tool which automatically synthesizes assertions and coverage properties and automates assertion and coverage based verification methodologies.

Insight targets several early RTL formal analysis applications that improve the quality of your RTL design and verification in several key areas, eliminate costly iterations, and improve overall schedule reliability. Existing solutions include formal reachability analysis, X-verification, low power verification, and At-Speed DFT testability.

The latest enhancement supports automatically synthesizing microarchitecture-level assertions and coverage that check hardware features and their interactions to detect design violations or uncover poor testsuite coverage.

“Microarchitecture assertions and coverage properties can isolate many problems and pinpoint the issue closest to their source. Automating assertion and coverage raises the baseline of verification planning leading to higher quality verification using objective measures while significantly reducing the effort level involved to implement compared to conventional, manual methods,” said Chilai Huang, president of Avery Design Systems. “The solution augments operational assertions manually developed by verification engineers for end2end verification and fills a gap for implementation-level assertions created by today’s ad hoc approaches.”

Based on symbolic analysis methods, Insight operates on block or chip-level RTL and automatically recognizes a rich set of microarchitecture hardware features including FSMs, queues, arbiters, counters, busses, complex control blocks, register and memory accesses, power design from UPF, and cross clock domain crossings. No testbench is required. High-level query functions report on microarchitecture design attributes and allows the user to control how to synthesize assertions and coverage properties.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of symbolic simulation and formal analysis for bug hunting and coverage closure, robust core-through-chip-level Verification IP for PCI Express, SATA, and USB standards, and scalable distributed parallel logic simulation. The company delivers software products to leading edge semiconductor and systems companies worldwide. Avery Design Systems is privately held. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with GDA Technologies, Snowbush, and Northwest Logic. Avery is a member of the PCI-SIG and USB Implementers Forum. More information about the company may be found at www.avery-design.com.