ANDOVER, Mass.-- January 24, 2011 --Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced it has developed a new capability for its Insight formal analysis tool which performs RTL At-Speed DFT coverage estimation and repair analysis. “Waiting to get at-speed path delay fault testability coverage estimates until after running ATPG exposes the chip project to costly and labor intensive design iterations to assess coverage, implement remedies, and confirm incremental coverage improvements”
.Insight targets several early RTL formal analysis applications that improve the quality of your RTL design and verification in several key areas, eliminate costly iterations, and improve overall schedule reliability. Existing solutions include formal reachability analysis, X-verification, low power verification, and microarchitecture-level assertion and coverage synthesis.
The latest enhancement addresses the significant rise in complexity in achieving adequate path delay fault coverage which can be typically much lower than the 1st pass stuck-at ATPG coverage results.
Improving stuck-at fault coverage can typically be improved through standard DFT design techniques such as adding scan wrappers or adding simple test mode controls. However improving path delay fault coverage may require making microarchitecture-level design changes which requires going back to the RTL code to add controllability and observability on a path-by-path basis.
“Waiting to get at-speed path delay fault testability coverage estimates until after running ATPG exposes the chip project to costly and labor intensive design iterations to assess coverage, implement remedies, and confirm incremental coverage improvements,” said Chris Browy, vice president of marketing at Avery Design Systems. “Addressing DFT earlier while the RTL is being developed allows issues to be uncovered earlier when they are much easier and quicker to fix.”
Insight’s RTL At-Speed DFT solution supports:
- High-level Tcl commands to describe scan design intent including how to apply memory bypass and shift register methods, include or exclude scan and X generators
- Reads SDC files for multi-cycle paths and false paths
- Performs first pass analysis to identify data stability issues associated with launch and capture cycles
- Analyzes testability based on intelligent sampling methods or user supplied paths and reports path-level testability and overall coverage
- Diagnoses untestables, generates and ranks repair solutions pinpointing exactly where to add controllability or observability for largest incremental coverage improvement
- Supports distributed processing for faster turnaround time
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of symbolic simulation and formal analysis for bug hunting and coverage closure, robust core-through-chip-level Verification IP for PCI Express, SATA, and USB standards, and scalable distributed parallel logic simulation. The company delivers software products to leading edge semiconductor and systems companies worldwide. Avery Design Systems is privately held. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with GDA Technologies, Snowbush, and Northwest Logic. Avery is a member of the PCI-SIG and USB Implementers Forum. More information about the company may be found at www.avery-design.com.