SAN MATEO, Calif. Following a trend among providers of RISC processor cores, ARC Cores Ltd. said it will introduce a real-time trace debug capability for its configurable 32-bit processor, the ARCtangent-A4.
Scheduled to be available in the first quarter of 2002, the on-chip debugger is intended to provide a history of instruction execution, data reads and writes, system events and execution timing and scheduling.
Moreover, the debugger works in real-time, so software developers are provided a more-detailed and accurate account of how their code performs under actual conditions, the company said.
A real-time simulator is becoming a critical element for code-heavy applications that would be impractical to debug using a conventional simulator, ARC said. The task becomes more burdensome as 32-bit RISC controllers run at higher frequencies, use larger caches and have hooks to more peripheral circuitry.
"An HDL simulator is measured in seconds/cycle vs. cycles/second," said Phil Barnard, product manager for ARC. "Imagine you have a Web camera generating images in real-time, compressing the image and shipping it out over USB. You don't know that you're getting 100 percent on a simulator because you can't run it in real-time."
One alternative is to resynthesize the processor and implement it in an FPGA. This will run the processor faster than a software simulator, but does not provide the visibility inside the core. "All those signals are inside the FPGA," Barnard said.
What ARC has done instead is bolt onto the processor extra functionality that collects and filters a trace history and sends it over to a workstation and logic analyzer in a compressed format all in real-time.
The idea is not unlike real-time trace functionality developed by ARM and IBM's PowerPC unit. But ARC claims its real-time trace has exceptionally good compression and is more flexible in terms of pin count and the type of information that can be traced.
The most crucial aspect of this approach is how compression is handled, ARC said, as this determines data throughput, the size of the FIFO buffer memory and how many extra pins will be needed for debugging. Without compression the processor would need to output 32 bits of information for every cycle. Yet ARC claims it can bring this down to an average of 1.3 bits per cycle by taking output data only when code gets ready to branch off and through various encoding techniques. This setup assumes that most code uses few branch points, though a buffer memory can be added if there are sections of code with many branches close together to prevent the system from overflowing.
"If you don't want to pay much for buffering and don't want to pay much for pins you have to have good compression," Barnard said.
With ARC's solution, each configurable processor can have as little as one or as many as 30 pins, and in some cases three cores on-chip can share as few as four pins. There's also no need for e xtra handshaking pins, said Barnard.
The FIFO, which is part of the trace core, can vary from 24-bytes to 1/2 kbyte. The FIFO tends to move toward the larger size if the developer wants to trace actual data such as for imaging that can't be compressed during a trace as instructions can.
ARC's trace unit takes anywhere from 20,000 to 40,000 gates on-chip, depending on the number of trace "triggers," filters and the size of the FIFO. The trace unit has been devised to track instruction, data and timing events, and can also be configured for miscellaneous trace occurrences like interrupts and external events.
A debugger that enables the real-time trace capability will be included as part of the company's Architect configuration tool, which uses a point-and-click user interface and generates the HDL or source code for the ARCtangent microprocessor. The trace data is fed to an external logic analyzer from a third-party test equipment provider, though ARC plans to provide its own captu re box by the middle of next year, Barnard said.