Cadence's Silicon Realization Approach Speeds Billion-plus Gate Design, Achieves 2X Performance Advantage in 28nm Routing
SAN JOSE, Calif., 31 Jan 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today advanced the design of giga-gate/gigahertz system on chips (SoCs) with a proven digital end-to-end flow at 28 nanometers that yields both performance and time-to-market advantages. Driven by the Cadence Silicon Realization approach, the new Encounter-based flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. Working seamlessly with Cadence’s analog/mixed-signal and silicon/package co-design domains, the new digital 28-nanometer flow enables designers to consider the entire chip flow holistically to drive breakthroughs in high-performance, low-power, mixed-signal, and even 3D-IC designs- critical success factors for mobility-based and multimedia SoCs.
The new flow, available immediately, supports Cadence’s approach to Silicon Realization through its focus on unique and pervasive design intent, abstraction, and convergence from RTL to GDSII, then through to packaging. Silicon Realization is a key element of the EDA360 vision.
“Twenty-eight-nanometer process technology is both a great opportunity and challenge for designers, with its power, performance and area advantages coupled with challenges such as process variation and new manufacturing effects,” said Albert Li, director of Design and Development at Global Unichip Corporation. “We used the Cadence digital end-to-end flow for our first 28-nanometer design because Cadence’s commitment to giga-gates/gigahertz design capabilities and advanced technology nodes is what we need to serve our customers. Using the Cadence digital end-to-end flow, we are able to not only handle the complex routing, variability and manufacturing requirements of 28-nanometer designs, but also tackle 100+ million gate designs within a reasonable design cycle time. The end result is more productivity and better schedule predictability on our deliverables to our customers.”
Eliminating the need for tradeoffs between complexity and advanced process nodes, the new flow optimizes complex design at 28 nanometers, providing a path for advanced SoC development to realize the cost benefits of smaller geometries. Key to the flow’s performance is a unified digital design, implementation, and verification based on intent, abstraction, and convergence.
Features that enhance unified intent include:
- Complete, silicon-proven 28-nanomter design rule intent (electrical, physical, DFM) with early, upfront tradeoff analysis, and a 2x improvement in routing runtime through intelligent via and pin-density optimizations
- Early clock topology intent capture and planning that uses physical information to intelligently optimize clock gating and balance clock trees throughout the design during synthesis
Features that enhance abstraction include:
- Breakthrough data abstraction technologies that enable entire blocks of logic to be modeled simply and accurately, and optimized across logical and physical domains, for giga-gate scalability and design productivity
- Support for hierarchical low-power and OpenAccess-based mixed-signal quick/detailed abstractions to enable rapid integration of IP and advanced SoCs
Faster convergence is achieved through such features as:
- A physically aware pre-mask functional ECO capability that automates difficult to implement functional ECOs, providing faster convergence and dramatically shortening the design cycle.
- A breakthrough architecture for in-design advanced analysis that provides ultra fast one-step signal integrity and timing analysis closure during the design flow for efficient design convergence
- Accurate full mixed-signal static timing analysis and timing-driven optimization to reduce iterations between analog and digital design teams
And new fully-integrated 3D-IC capabilities with unified intent, abstraction, and convergence spanning digital, full-custom, and package design, now enable optimized performance, size, cost and power.
“The complexity of 28-nanometer design coupled with the need to support complex giga-gate/gigahertz requirements demands an integrated end-to-end flow,” said David Desharnais, senior director, Silicon Realization product marketing. “Our unique Silicon Realization approach allows our customers to push their SoC designs to new levels in order to deliver the highest performance silicon for multimedia, communications and computing applications. Today’s announcement of our comprehensive 28-nanometer digital Silicon Realization flow continues our push toward realizing the EDA360 vision.”
The Encounter-based Silicon Realization digital end-to-end flow includes technologies such as Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Conformal technologies, Encounter Test, Encounter Timing System, Cadence QRC Extraction, Encounter Power System and Encounter DFM technologies.
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.