CPM v2.0 Delivers Greater Coverage and Enhanced Usability for Chip-Package-System Co-analysis and Co-optimization
SAN JOSE, Calif.-- January 31, 2011 --Apache Design Solutions, providing the industry’s leading power and noise solutions for Chip-Package-System (CPS) convergence from RTL to sign-off, announced the release of CPM v2.0, its next generation Chip Power Model (CPM) intended for true co-analysis/co-optimization of the chip, package, and system. Ideal for wireless and automotive markets, including 3D IC and SiP designs, the release of CPM v2.0 expands the range of coverage to include system resonance awareness, the power transition impact on a global power delivery network (PDN), thermal co-analysis, and EMI and EMC validation. It also delivers user configurable models for an effective CPS flow.
“Apache pioneered the market with its first delivery of CPM, and as adoption and application of the model continues to grow, our close partnership with customers has driven us to provide more advanced features to meet their needs,” said Andrew Yang, CEO of Apache Design Solutions. “Our franchise in the IC power domain and the market leadership of RedHawk has provided Apache with the unique position to deliver the most comprehensive, accurate, and usable die model for chip-package-system convergence.”
Broader Range of Applications
Apache’s resonance-aware CPM v2.0 model considers the LC resonance frequency of the system and automatically generates an on-die switching scenario operating at or near the system resonance. This unique capability enables system designers to access a CPM representing the worst case switching scenario that can be used for stress testing the CPS design. By using resonance-aware models, designers can determine the optimal placement and configuration of the package and PCB decoupling capacitance to help manage power and noise.
CPM v2.0 models on-die power transient waveform over a long duration to capture the envelope modulating the high frequency switching. This represents middle to low frequency components on the chips which impacts the global PDN and needs to be handled by package and PCB power supply system. The power transition model allows system designers to simulate load step conditions to identify and debug weaknesses in their package and system designs.
In 3D-IC and SiP designs, thermal integrity becomes a major challenge for chip-package-system co-design. The power mapping in CPM v2.0 enables package designers to accurately predict the thermal distribution and hot spots of multiple die in a stacked die packaging.
In automotive and wireless markets, using on-chip LDO voltage regulators is increasing, but a key design concern is EMI and EMC. The expanded capability of CPM v2.0 delivers a power model that contains the LDO circuitry that is critical to system-level EMI and EMC validation.
Apache’s CPM v2.0 offers enhanced usability with user configurable models for system-level ‘what-if’ analysis of various IC switching scenarios. Chip designers can create multiple current profiles for various blocks within the design, enabling system designers to simulate power switching scenarios and exhaustively verify their system.
In addition, CPM v2.0 adds probing of internal nodes for interactive dynamic power analysis. This provides system designers with access to the critical areas of chip for enhanced debugging and optimization.
About CPM v2.0
Since Apache first introduced CPM in 2007, the industry’s first compact die power model has been widely adopted as the key enabler for CPS co-analysis by semiconductor and system design companies. The first generation compact model represented full-chip PDN with distributed on-die power and ground resistance, decoupling capacitance, and inductance of the digital core, memories, and IP. The release of CPM v2.0 adds considerable advancements to help meet the increasing accuracy and usability requirements of system designers.
For example, system designers can explore the addition of decoupling capacitance at a high power node of the IC to reduce the dynamic voltage drop, instead of adding them onto the package, which can result in higher costs. This flexibility allows system designers to make educated co-optimization decisions without an iterative loop of requesting an updated model from IC designers.
About Chip Power Model
CPM is a compact and Spice-accurate model of the full-chip power delivery network. It contains spatial and temporal switching current profile, as well as parasitics of non-linear on-chip devices including decaps, loading capacitance, and power/ground coupling capacitance. CPM represents the entire die power delivery network with ports at the die level C4 bumps and/or pads. It accurately models the electrical response of the chip for a wide range of frequency, from DC to multi-GHz, thus enabling the analysis, diagnostics, and optimization of system-level power integrity designs.
Pricing and Availability
Apache’s release of CPM v2.0 is available on the market today. For existing Apache RedHawk-CPM customers, CPM v2.0 is available as a no cost upgrade. Contact your local Apache sales representative for more information.
About Apache Design Solutions
Apache delivers the industry’s leading power and noise solutions for chip-package-system convergence from RTL to sign-off. Apache's innovative platforms address the unique power and noise challenges associated with specific design domains such as digital, analog and mixed-signal, IC package and PCB, while providing a co-analysis environment that integrates the SoC, custom IP, and System worlds. From RTL power analysis and reduction, to early stage prototyping and optimization, and through chip and package sign-off, Apache’s products enable designers to lower power consumption, increase operating performance, reduce system cost, and mitigate design risks. Apache is a global company with R&D centers and direct sales and support offices worldwide and their products are adopted by all of the top semiconductor companies.