Cadence exec: EDA needs 'breakaway value'
Peter Clarke, EETimes
2/2/2011 11:31 AM EST
SANTA CLARA, Calif. – EDA has got a challenge on its hands, but that is one of the things that attracted John Bruggeman to join Cadence Design Systems Inc. as chief marketing officer. He was previously CMO with embedded software company Wind River Systems.
Bruggeman, speaking to EE Times at the DesignCon conference here, reckons there is a lot of churn in the EDA market as difficult, expensive or even failing projects are causing semiconductor companies to throw out incumbent suppliers and try a different design flow. The complexity of design at 40-nm, 28-nm and down to 20-nm is also driving a transition from a pick-and-mix best-in-class approach to a single supplier or few supplier strategy, Bruggeman said. And, of course, such changes and the negotiations associated with them, are one of the mechanisms by which the chip companies bear down on the pricing.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
Related News
- Thalia's IP reuse platform joins Cadence Connections EDA Program
- Cadence Introduces the EDA Industry's First Verification Solution for PCI Express 3.0
- Cadence Design Systems Appoints John Bruggeman as Chief Marketing Officer
- Cadence Incisive Verification IP Portfolio Delivers 'All-in-One' Flexibility and Higher Value for SoC Developers
- Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry's SF4, SF3E and SF3 Process Technologies
Breaking News
- IAR Systems fully supports the brand-new Industrial-Grade PX5 RTOS
- Axiomise Accelerates Formal Verification Adoption Across the Industry
- Fluent.ai Offers Embedded Voice Recognition for Cadence Tensilica HiFi 5 DSP-Based True Wireless Stereo Products
- intoPIX to feature TicoXS FIP technology for premium 4K & 8K AVoIP wireless AV at ISE 2023
- Sevya joins TSMC Design Center Alliance
Most Popular
- Weebit Nano nears productisation, negotiating initial customer agreements
- Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry's SF4, SF3E and SF3 Process Technologies
- Sevya joins TSMC Design Center Alliance
- Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
- Open Compute Project Foundation and JEDEC Announce a New Collaboration