New NurLogic, Get2Chip Program Targets System-On-Chip Designers Designers Can Access Powerful Library, Architectural Synthesis Combination
SAN DIEGO & SAN JOSE, Calif.--(BUSINESS WIRE)--Nov. 6, 2001--NurLogic Design, Inc., a developer of high-bandwidth connectivity Intellectual Property (IP) solutions, and Get2Chip Inc., the electronic design automation (EDA) supplier of system-on-chip (SOC) synthesis, today launched a program where physical library models are bundled with architectural and RTL synthesis.
The distribution program is designed to give hardware designers access to an EDA software evaluation kits that includes qualified standard cell and standard input/output (I/O) libraries. This marks the first time NurLogic has authorized an EDA software supplier to use its front-end intellectual property (IP) models for synthesis.
"NurLogic's goal is to get our high-performance libraries into the hands of designers to help alleviate the ever-increasing challenges of SOC design," says Lisa Lipscomb, vice president of marketing at NurLogic. "We chose to work with Get2Chip because of the success of its architectural synthesis and its focus in the area of timing abstraction."
"Our customers tell us there is a lack of qualified and reliable IP providers," remarks Steve Carlson, Get2Chip's vice president of marketing. "NurLogic addresses this problem with its silicon-proven IP solutions. We view NurLogic as an important strategic partner."
Get2Chip, Inc., is a leading supplier of software products that enable the design of the world's most complex integrated circuits, primarily found in the communications, wireless, computer, and consumer product markets. It was launched in 2000 by semiconductor veterans and chip design tool experts from Cadence Design Systems, Inc. (NYSE: CDN - news), LSI Logic Corporation (NYSE: LSI - news), Mentor Graphics Corporation (Nasdaq: MENT - news), Synopsys (Nasdaq: SNPS - news) and VLSI Technology -- now part of Philips Semiconductors (NYSE: PHG, AEX: PHI). Its breakthrough front-end tool suite, VOLARE(TM), provides fully integrated, multi-level synthesis that offers the flexibility to do chip design at the architectural, register transfer (RTL) or gate level. Its TOPOMO(TM)product integrates and automates block partitioning, block placement, global routing and synthesis into one front-end integrated circuit (IC) design tool. Both run on SUN, PC under Linux, and HP. Get2Chip is privately held and has development centers in San Jose, Calif., and Munich, Germany. Corporate headquarters: 2107 North First Street, Suite 350, San Jose, Calif. 95131. Telephone: (408) 501-9600. Facsimile: (408) 501-9610. Email: email@example.com. Web Site: http://www.get2chip.com.
About NurLogic Design, Inc.
NurLogic Design, Inc. provides high-bandwidth connectivity solutions to the networking and communications industries. NurLogic's products encompass customer-specific and industry-standard integrated circuits and semiconductor intellectual property to deliver value-add to its customers. NurLogic products are targeted at CMOS and silicon germanium technologies, and include high-speed connectivity IP, analog and mixed-signal IP, foundation IP, and PMD and PHY ICs. Based in San Diego, California, the company has regional sales offices in Massachusetts and Silicon Valley. NurLogic is a privately held corporation. Headquarters: 5580 Morehouse Drive, San Diego, Calif. 92121. Tel: 1-877-NURLOGIC. On the web at www.nurlogic.com.
NurLogic is a trademark of NurLogic Design, Inc. Get2Chip and VOLARE are trademarks of Get2Chip. Get2Chip and Nurlogic acknowledge trademarks or registered trademarks of other organizations for their respective products and services.
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