USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, 7nm, 6nm)
Novocell Semiconductor, Inc. to Provide OTP Solution Across Multiple IBM Foundry Semiconductor Process Nodes
Hermitage PA, February 14, 2011 -- Novocell Semiconductor, Inc., today announces it will provide one-time programmable (OTP) memory solutions spanning fourteen different IBM Foundry Semiconductor processes. Novocell will qualify its OTP memory in the 350, 250, 180, 130, and 90nm IBM nodes.
“Novocell is pleased that IBM has selected our unique technology for migrating a core OTP solution over multiple nodes and process variants,” said Steven Warner, Novocell’s CEO/President.
Novocell provides a fully enabled, drop-in array that is programmable with standard I/O inputs, no special pins or optional charge pumps are required. 100% reliability is assured through NovoBlox’s unique SmartBit technology that provides real-time, programming feedback. NovoBlox OTP will provide IBM with an area-saving, reliable compliment to the IBM e-fuse.
About Novocell Semiconductor, Inc.:
Novocell Semiconductor, Inc., specializes in developing and delivering advanced non-volatile memory intellectual property (IP) to the semiconductor industry. Novocell is the only provider of 2nTP, the first multi-time write antifuse memory IP. NovoBlox OTP and 2nTP are the reliability leading antifuse memories proven to have zero tail bit failures within operating ranges and 30 years of data retention. The technology is available and is scalable from 350nm to 45nm and beyond. For more information, please visit: www.novocellsemi.com.
|
Silicon Storage Technology, Inc. Hot IP
Related News
- Novocell Smartbit Antifuse OTP NVM Memory Validated at IBM Foundry at Processes from 350nm to 130nm
- Cosmic Circuits announces portfolio of Analog-to-Digital Converter IP-cores for Monitoring Applications across multiple process nodes
- Siemens extends support of multiple IC design solutions for Samsung Foundry's latest process technologies
- Samsung Foundry Certifies Synopsys PrimeLib Unified Library Characterization and Validation Solution at 5nm, 4nm and 3nm Process Nodes
- Cadence Collaborates with Samsung Foundry to Accelerate Hyperscale Computing SoC Design for Process Nodes Down to 4nm
Breaking News
- IAR Systems fully supports the brand-new Industrial-Grade PX5 RTOS
- Axiomise Accelerates Formal Verification Adoption Across the Industry
- Fluent.ai Offers Embedded Voice Recognition for Cadence Tensilica HiFi 5 DSP-Based True Wireless Stereo Products
- intoPIX to feature TicoXS FIP technology for premium 4K & 8K AVoIP wireless AV at ISE 2023
- Sevya joins TSMC Design Center Alliance
Most Popular
- Weebit Nano nears productisation, negotiating initial customer agreements
- Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry's SF4, SF3E and SF3 Process Technologies
- Sevya joins TSMC Design Center Alliance
- Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
- Open Compute Project Foundation and JEDEC Announce a New Collaboration
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |