Innovative tool and plug-and-play IP improvements which leverage open industry standards accelerate design creation, verification, implementation, and lower system power.
SAN JOSE, Calif., March 8, 2011 -- Xilinx, Inc. (Nasdaq: XLNX) today announced the immediate availability of ISE(R) Design Suite ISE13. New to the award winning design tool and IP suite are enhancements which improve productivity across SoC design teams and progression towards true plug-and-play IP that targets Spartan(R)-6, Virtex(R)-6 and 7 series FPGAs, including the industry-leading 2-million-logic-cell Virtex-7 2000T device. Focusing on decreasing development time and cost, ISE Design Suite 13 introduces accelerated verification, plug-and-play IP with IP-XACT Support and a new team design methodology that shortens design cycles with timing repeatability for multiple engineers working in parallel.
As Xilinx delivers FPGAs with multi-million system gate capacities, such as the Virtex-7 2000T device built using Stacked Silicon Interconnect technology, as well as capabilities to combine serial, parallel and digital signal processing on a single chip, and offer transceiver speeds of up to 28 Gbps, the need for productivity is paramount in these highly complex designs.
To stay on the productivity curve, however, the industry needs to achieve 50 percent cycle time improvement according to the International Technology Roadmap for Semiconductors.
With over half of the design cycle spent in verification, the ISE Design Suite 13 new hardware Co-Simulation capability and AMBA(R)4 AXI4 (Advanced Extensible Interface) bus functional simulation models provide direct productivity gains for design verification teams.
Leveraging Xilinx's large portfolio of development boards, kits and Xilinx's ISE Simulator, design teams can now accelerate simulation runs that previously would take hours into minutes. Through real-time simulation, verification engineers can test implemented blocks of the design while leaving other blocks that are still under development in the simulator accelerating overall verification by up to 100 times faster than native simulation. The new optional AXI4 bus functional model can also be added to verification test benches to drive stimulus and to validate interconnect logic of customer supplied IP improving overall productivity.
New Team Design Flow
Also new to ISE Design Suite 13 is a team design methodology (See Increased Productivity Using Team Design) which addresses the challenge of multiple engineers working on a single project by providing a methodology for group of developers to work in parallel.
"The complexities of designing SoC's can require an international team of developers working on a single design. Not only are multiple engineers developing HDL, but a separate engineer might be an integrator responsible for the synthesis and implementation of the entire system design. To make matters more challenging, the team can be composed of several companies which develop different modules of the design," said Tom Feist, Senior Director of ISE Design Suite Marketing.
Building on the Design Preservation capability made available in ISE Design Suite 12, the team design flow provides additional functionality and allows early implementation results on completed portions of the design to be locked down without having to wait for the rest of the design team. This new capability supports advanced optimizations including intelligent clock gating that can provide up to 30 percent dynamic power reduction, facilitates faster timing closure and timing preservation for the remainder of the design increasing overall productivity and reducing design iterations.
Plug-and-play IP with IP-XACT Support
Accelerating design reuse, the new ISE Design Suite 13 suite now delivers new open standards in line with Xilinx's plug-and-play initiative (See AXI4 Interconnect Paves the Way to Plug-and-Play IP) and shortens design creation times by easing development with Xilinx and third party IP. New in this release is a configuration option to the AXI interconnect that allows a 50 percent reduction in the interconnect silicon footprint using sparsely connected AXI4 interconnect. For high performance AXI4 systems, customers can get up to 20 percent higher system bandwidth for interconnect and memory interfaces. Users can now easily customize their system for either performance or area to achieve optimal system topology.
Also provided is a new IP-XACT based IP Packager for Xilinx Alliance Program Members. IP-XACT based IP Packager from Xilinx enables an Alliance Member to package their IP so that it can be easily accessed out of the CORE Generator(TM) IP repository. IP-XACT enables a consistent user experience for using IP from both Xilinx and its Alliance Program Members. In ISE Design Suite 13, 50 Xilinx IP cores support IP-XACT and within a year, all Xilinx IP cores will support IP-XACT. Future releases will open this same capability to customers for easy design reuse of their IP.
"It is critically important that our customers are able to easily understand and use our IP," said Brian Daellenbach, President of Northwest Logic, a Premier Xilinx Alliance Program Member. "With the new IP Packager in the ISE Design Suite, we can now provide our IP with the same CORE Generator environment that customers are familiar with. This enables customers to more quickly and easily configure and use our IP in their designs."
To make it easier for users to simulate encrypted IP, Xilinx is the first company to offer an IEEE P1735 compliant simulation model for the AXI BFMs supporting AXI3 or AXI4 protocol for simulation interoperability with major third party simulators. A fully functional IEEE P1735 encryption flow for Alliance Program Members will be available later this year.
For applications such as wireless baseband, video and beam forming that require linear algebra mathematics to be implemented a new highly configurable Linear Algebra LogiCORE(TM) IP core is now available inside CORE Generator. The IP core implements matrix operations, such as: matrix addition, subtraction, multiplication, and matrix-scalar multiplication.
Additional processing support for embedded systems design in ISE 13 is delivered with a new high assurance MicroBlaze(TM) processor. In systems that require redundancy and fault detection, the high assurance MicroBlaze processor provides memory protection and the capability to have redundant MicroBlaze processors with lockstep for meeting high assurance and reliability requirements. By providing the processor and comparator logic in an integrated easy to use IP block, designers can securely design the soft-core MicroBlaze processor into secure applications such as ATMs that frequently require error detection.
New Documentation Navigator
The new Xilinx Documentation Navigator vastly improves key facets of Xilinx documentation management, including viewing, discovering, searching, and downloading.The Navigator brings Xilinx FPGA device, software, boards and targeted reference design documentation into a single, easy to use environment. The standalone tool focuses on improving customer productivity and ensuring customers that they can get to their answer quickly. The Xilinx Documentation Navigator is available for download at: www.xilinx.com/support/documentation/
Availability & Pricing
ISE Design Suite 13 is immediately available for all ISE Editions and list priced starting at $2,995 for the Logic Edition and now supports 32- and 64- bit Windows 7. Customers can download full-featured 30-day evaluation versions at no charge from the Xilinx web site. To get started today with the ISE Design Suite 13 software release or for more information about the power and cost-saving design methodologies and productivity innovations introduced in ISE Design Suite 13, visit: www.xilinx.com/tools/designtools.htm.
Xilinx is the world's leading provider of programmable platforms. For more information, visit www.xilinx.com/.