Dolphin Integration announces a density record for Dual Port Register Files saving up to 30% of area
Grenoble, France – April 1, 2011. The innovative ERIS architecture for Dual Port Register Files is the attractive alternative to conventional Dual Port memory generators at 130 nm.
The DpRFolder™ ERIS (2R/2W) allows power and cost reductions, while satisfying the speed constraint of many high-speed applications from high-density consumers and portable devices.
Highlights
Reduced die cost
- Up to 30% denser than older solutions on the market
- Optional High Density BIST for industrial test of instances
- Layout compatibility between various foundries
The easiest integration in your SoC
- All the flexibility of 2 independent read and 2 independent write ports (2R/2W)
- Library of synthesizable models through StorageWare™ for facilitating the selection and integration of small memories
The Dolphin quality
- Guaranteed design yield for the memories in your circuits
Have a quick look at the Presentation Sheet.
To request an access to the DpRFile ERIS generator, click here
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/ragtime
|
Dolphin Design Hot IP
Related News
- Dolphin Integration launches a 65 nm compiler for Dual Port Register Files reaching the highest density
- Dolphin Integration introduces an ultra High Density Library decreasing the 130 nm logic area up to 30%
- Dolphin Integration breakthrough innovation for TSMC 180 nm BCD Gen 2 process: Up to 30% savings in silicon area with the new SpRAM RHEA
- Dolphin Integration introduces a new Panoply of Silicon IPs for reducing the 65 nm silicon area up to 10%
- Dolphin Integration launches a standard cell library with ultra-high density up to 30% savings
Breaking News
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PiMCHIP Deploys Ceva Sensor Hub DSP in New Edge AI SoC
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
Most Popular
- DENSO and U.S. Startup Quadric Sign Development License Agreement for AI Semiconductor (NPU)
- Xiphera and Crypto Quantique Announce Partnership for Quantum-Resilient Hardware Trust Engines
- Arm's power play will backfire
- Alchip Announces Successful 2nm Test Chip Tapeout
- Faraday Unveils HiSpeedKit™-HS Platform for High-speed Interface IP Verification in SoCs
E-mail This Article | Printer-Friendly Page |