MIPS Technologies plans to make its processors more configurable. The approach will be one strand of a mixture of parallelism and multiprocessing techniques the company will use as it shifts emphasis to the high end of the cores market.
Keith Diefendorff, who has joined MIPS from configurable cores specialist ARC International as vice-president of product strategy, says the moves will take advantage of a gradual move towards software-programmable cores in place of hardwired logic. This will reduce the time it takes to get working designs into place.
He said: "We are doing several things. We are investing heavily in defining high-performance cores. As a component of that, we do have a configurability option. And we will be incorporating UDIs [user-definable instructions] into our cores."
Kevin Meyer, MIPS' vice-president of marketing, added: "There is nothing inherent in the architecture that prevents [configurability]. We jus t have not done it to date."
He says the company has experience in defining instructions for vertical markets, and cites extended versions of its core such as MIPS16, MIPS3D and SmartMIPS: "We have supported vertical markets without burdening the implementation."
MIPS has cut a deal with Toshiba that will produce a core with additional instructions. Toshiba is one of only a few companies so far given the leeway to add instructions — DSP operations in its case — to the core MIPS instruction set architecture.
"We have the hooks and we will put them in to support UDIs in the future," said Meyer. "We are also putting in the software infrastructure to support that."
He says it is too early to say publicly how MIPS will control licensees' use of UDIs or which cores would benefit most.
Meyer added: "It will help keep our 32bit cores competitive from this point forward. Keith brings experience of how to do this without fragmenting the architectu re."
Diefendorff said: "One of the advantages that MIPS has is that the architecture has remained remarkably clean. It makes highly parallel implementations of the MIPS architecture much more easy to create."
The company will add vector operations to extend the processor architecture's portfolio of single-instruction, multiple-data operations.
"We have to be careful about how it is done," he said. "We will preserve the cleanliness of the architecture but take advantage of vector operations."
"In the applications we see in the embedded space, there are a number of types of parallelism. For example, there are data parallelism and thread-level parallelism.
"We anticipate taking maximum advantage of all of the different types of parallelism, such as multithreading.
"Part of the problem is that the software technology necessarily to parallelise single-threaded applications, only some of that exists. We can build hardware that takes advantag e of that over time. Then there is explicit parallelism that the OS can launch easily."
Diefendorff said the company will build hooks into the architecture so that the processor does not depend on the OS scheduling thread but can take "hints" from the software of what to run when.
"It is a chicken and egg situation. So, we will put the [multithreading] support in and as the software learns, we will build techniques to exploit it."
The remaining form of parallelism that the company expects to support is on-chip multiprocessing, a technique already used by licensees such as PMC-Sierra.
Diefendorff said: "Different styles of chip multiprocessing will be called for and all will be used [somewhere]. It depends on the application."