NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
SystemC reference manual running slightly behind schedule
![]() |
SystemC reference manual running slightly behind schedule
By Peter Clarke, EE Times
March 6, 2002 (4:49 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020301S0076
PARIS The Open SystemC Initiative (OSCI) is expected to announce at the Design Automaton and Test in Europe (Date) conference that it is pushing ahead with production of a language reference manual (LRM) for SystemC. But the LRM may arrive up to one year later than OSCI had originally planned.
SystemC is a C++ class library and modeling platform being developed for design and verification work beyond the scope of today's HDLs. It has backing from a number of EDA vendors, and OSCI is also aiming for eventual IEEE standardization of the language.
OSCI is preparing to announce at this year's Date conference, which begins Monday (March 4), that it has contracted Paul Menchini, of Menchini and Associates, to develop the LRM for delivery later in 2002. However, the OSCI Web site states that the language's LRM was due " late in 2001."
"Ultimately, delay from original plan occurred due to mundane organizational things like ramp up of OSCI finances and from OSCI being everyone's "second job," said Kevin Kranen, director of strategic programs at Synopsys Inc. and president of OSCI. "No one should be disadvantaged by delay as all have had access to the 'gold standard' for SystemC v2.0, the actual reference implementation, since last July."
Delivery of the LRM is expected to be OSCI's first step towards standardization of SystemC by the IEEE. OSCI expects to present the language to the IEEE for standardization within two years.
Related News
- Accellera Systems Initiative advances the SystemC ecosystem with a new core language library
- Reference Virtual Platform of ARM Model Running Linux Under SystemC/TLM-2.0 Released by Open Virtual Platforms (OVP)
- Accellera Announces Relicensing of SystemC Reference Implementation under the Apache 2.0 License
- intoPIX Showcases a SMPTE2022 Reference Design running on Xilinx FPGA and enabling Live Video over IP transport using JPEG2000
- ARM Cortex-M3 Reference Platform Running Micrium uC/OS II Released On OVP
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |