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England's Jennic rolls out IP cores for ATM networks
By Semiconductor Business News
March 1, 2002 (11:49 a.m. EST)
URL: http://www.eetimes.com/story/OEG20020301S0057
SHEFFIELD, England -- Jennic Ltd., a supplier of intellectual-property (IP) cores, here rolled out new additions to its family of ATM segmentation and reassembly (SAR) chip engines. The new cores extend the bandwidth of its Modular ATM Segmentation And Reassembly (SAR) family to 622-megabits-per-second (Mbps), from 155-Mbps in previous versions, according to the Sheffield-based company. "By continuously enhancing and expanding the Modular SAR family, we now offer our access customers an easy way of sourcing all their ATM transport needs," said Jim Lindop, Jennic's CEO. The Modular SAR family facilitates transport of digital video, voice and data via ATM networks. The programmable hardware implementation is specifically designed to target low-power and low-cost broadband Internet access solutions. Applications include xDSL and ATM-over-passive optical network (APON) home gateways, and office local and wide area network hub and network interfac e devices. The highly-configurable Modular SAR products are based on a 102,000 gate core, which includes dedicated support for real-time data interfaces that bypass the host processor. ATM Adaptation Layer 0, 1, 2 and 5 are supported at full line-rate, with traffic shaping for constant bit rate (CBR), variable bit rate (VBR) and unspecified bit rate (UBR) service classes. The modular design facilitates the integration of ATM functionality into an end system, allowing customization for the target application. A number of host interfaces are available, enabling optimal integration with a variety of processors. For example, with AHB interface and 16 VCs, the total dimensions of an integrated Modular SAR, including RAM, are around 1.8 x 1.8 mm² when manufactured in a typical 0.18-micron process.