NVM OTP in UMC (180nm, 153nm, 110nm, 90nm, 80nm, 55nm, 40nm, 28nm, 22nm)
Dolphin Integration enables 1P3M/1P4M SoC designs at 180 nm with their ultra high density standard cell library
Meylan, France – May 16, 2011. Celebrated for its cost reduction capability by designers of high volume devices at 180 nm, the standard cell library SESAME uHD-BTF is the best solution whatever the number of metal layers in a SoC implementation!
SESAME uHD-BTF incorporates the latest architectural innovations from Dolphin Integration, replacing classical flip-flops with their “spinner cell”. The Ultra High Density cells leave metal 2 free to ensure more efficient place and route.
The benefit of such innovations is a significant improvement in terms of density and power consumption compared to standard 7-Track libraries at 180 nm: uHD-BTF is up to 30% denser and half as consuming!
The uHD-BTF library also enables to reduce significantly the overall die-cost of applications requiring the use of 1P3M or 1P4M for physical reasons such as in image sensors, and for cost reduction such as in power metering.
Highlights:
- Reduced die cost
- Metal 1 only is used for cell design
- Specific High Density Flip Flop
- Ultra low Dynamic
- Half as consuming by design as foundry-sponsored solutions
- A Low Voltage and a Dual Voltage variants are also available
Have a look at the Product Brief.
Due to the diversity of foundries addressed, make sure to ask for your preferred foundry and process variants and shrinks.
To appreciate the high-density performance of our Standard Cell Library, do not hesitate to proceed through an evaluation: contact directly the product manager at sesame@dolphin.fr
About Dolphin Integration
Dolphin Integration is up to their charter as the most adaptive and lasting creator in the Microelectronics Design Industry to "enable mixed signal Systems-on-Chip". It stars a quality management stimulating reactivity for innovation as well as independence and partnerships with Foundries. Their current mission is to supply worldwide customers with fault-free, high-yield and reliable sets of CMOS Virtual Components. The strategy is to follow product launches with evolutions addressing future needs, emphasizing resilience to noise and drastic reductions of power-consumption at SoC level, thanks to their own EDA solutions enabling Integration Hardware Modeling (IHM) and Application Hardware Modeling (AHM) as well as early Power and Noise assessment, plus engineering assistance for Risk Control. For more information about Dolphin, visit: www.dolphin.fr/ragtime
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