Industry Support Builds for Intel"s Formal Property Verification Language Initiative Synopsys, Verisity Design and Co-Design Automation to Adopt Intel's ForSpec
SANTA CLARA, Calif.--(BUSINESS WIRE)--Nov. 5, 2001--Intel Corporation today announced that three electronic design automation (EDA) companies have agreed to adopt Intel's functional verification assertion language (ForSpec). Synopsys, Verisity Design and Co-Design Automation will adopt ForSpec for their future functional verification EDA tools. Intel has extensive expertise in formal verification and has submitted ForSpec to the formal standards organization, Accellera, which is chartered with defining a standard formal property verification language for consideration, adoption and eventual transfer to IEEE.
"Formal property verification represents the next major advancement in functional verification for complex integrated circuits," said Greg Spirakis, vice president of Intel's Design Technology. "The electronic design community is looking for a standard formal assertion language to begin deploying new tools and methodology. Having a standard language will enable design reuse and speed tool integration."
Synopsys will incorporate the ForSpec language into OpenVera* to provide the OpenVera community with a powerful verification solution based on Synopsys' testbench automation tool, VERA*. OpenVera is an open source hardware verification language that enables seamless interoperability among verification tools, ease of use through an integrated verification methodology, and open distribution of verification intellectual property. The addition of ForSpec includes Intel's formal verification capabilities in an open language that drives both property verification and Synopsys' high performance simulators, VCS* and Scirocco*.
Verisity Design also plans to incorporate the temporal logic portion of ForSpec into the e verification language. By incorporating the ForSpec temporal logic into the e language, Verisity will enable a more powerful, streamlined verification methodology combining Intel's formal verification capabilities and Specman Elite*. Verification of today's complex systems, system-on-chip (SoC) and large ASIC designs requires a single specification of intended behavior to integrate these verification technologies into a workable system. Such a verification environment enables engineers to get the best leverage from both formal and simulation engines.
Co-Design Automation has agreed to merge the ForSpec temporal constructs into their SUPERLOG* design and verification language. This will enable a powerful property verification mechanism implemented in a manner recognizable and usable by Verilog designers as well as verification engineers. SUPERLOG, incorporating ForSpec, will enable an effective combined simulation and property verification methodology that can be applied across the entire design and verification flow, while improving the ease of use of property verification technologies in practical design processes.
As part of the ensuing development of ForSpec, Synopsys, Verisity and Co-Design Automation are contributing enhancements to the new formal property verification language that will be submitted to Accellera for the final phase of its standards selection process.
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