New logiMEM_arb Memory Controller IP core
New Xylon's memory controller IP core fully utilizes Xilinx® Memory Controller Blocks (MCB) in Xilinx Spartan®-6 FPGAs
Zagreb (Croatia) -- June 1, 2011 – The new Xylon’s logiMEM_arb memory controller and arbiter IP core allows users to easily connect SDRAM, DDR, DDR2, DDR3, or LPDDR memories to FPGAs. Designed specially for Xilinx Spartan-6 FPGAs, the IP core fully utilizes Xilinx’s MCB embedded block multi-port memory controller hard IP cores and enables the maximum achievable memory bandwidths of up to 6.4 GB/sec.
This memory controller supports a total of up to 16 ports for on-chip processor and peripheral IP connections, and by means of memory interleaving, simultaneous memory accesses of up to 8 IP cores. The simultaneous memory accesses greatly improve memory bandwidth utilization of external SDRAM devices. The IP core can use all available MCBs within the certain Xilinx Spartan-6 chip.
Controller’s ports for IP connections are very programmable. Users can configure the ports to support different on-chip bus standards: AMBA® AXI4, CoreConnect Processor Local Bus (PLB), Xilinx Cache Link for Xilinx’s soft-CPU MicroBlaze(TM) cache interface, Xilinx Native Port Interface (NPI) and Xylon Memory Bus (XMB).
Just like all other Xylon logicBRICKS IP cores, the logiMEM_arb memory controller and arbiter IP core is fully compatible with the Xilinx Platform Studio and the EDK integrated software development tools. FPGA designers can setup the IP core configurations through a GUI, optimize feature sets and control the utilization of FPGA resources, and in a drag & drop fashion, implement Xilinx SoC without hand coding.
For datasheet and general information about the logiMEM_arb Memory Controller and Arbiter IP core please visit:
The logiMEM_arb IP core is used in the logiTAP Platform for Embedded GUI Developments platform’s reference design.