New Flows Address Software Development, System Design, Co-Verification
OXFORD, United Kingdom, June 3, 2011 – Imperas™ today announced that its Open Virtual Platforms™ (OVP™) OVPsim simulator and OVP Fast Processor Models™ have been integrated with Aldec’s Hardware Emulation Solutions (HES), Cadence Design System’s Virtual System Platform and Proximus’ products. OVP’s position as the de facto source of instruction accurate processor core models provides additional value in the hardware-software co-verification, SystemC simulation, software development and system design flows supported by these tools.
The OVP Fast Processor Models and OVPsim are available from the Open Virtual Platforms website, www.OVPworld.org. The nearly 60 models available include models of the ARC 6xx/7xx families, ARM 7, 9, 10, 11, Cortex-M and Cortex-A families, MIPS Technologies 4K, 24K, 34K, 74K, 1004K, 1074K and M14K families, Power Architecture E200 cores and Renesas (NEC Electronics) V850 cores. All models have shown exceptionally fast simulation performance of hundreds of millions of instructions per second.
As SoCs have become increasingly complex, both in terms of the hardware design and the software stack delivered with the silicon, emulation of the SoC has become more widely used as a verification tool. The Aldec HES product, with its Transaction Level emulation System, integrates easily into existing RTL verification flows, providing both simulation acceleration and hardware emulation functionality.
“The integration of HES with OVPsim enables hardware and software design teams to implement virtual models of processors, memory and peripherals while the RTL modules run in the emulator board,” said Zbyszek Zalewski, general manager of Aldec’s Hardware Division. “This new integration provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.”
The Cadence Virtual System Platform is a software development platform that utilizes Cadence’s industry leading Incisive Verification Platform, particularly the SystemC simulation and debug environment. It adds multiple views of the hardware and software, assisting not only software development but also system analysis. The OVP Fast Processor Models have been integrated with the Virtual System Platform, not only providing simulation of the processor cores but also connecting to the Cadence debug tools. In addition, the Imperas Multicore/Multiprocessor Verification, Analysis and Profiling (M*VAP™) tools have been enabled to run in the Virtual System Platform environment. The M*VAP tool suite includes tools for embedded software development, such as code coverage, tracing, profiling and memory and cache analysis. These tools are completely non-intrusive, requiring no instrumentation or modification of the software source code, and are both CPU and OS aware.
The Proximus products together provide a suite of tools for system design and software development. These products provide an environment for analyzing the complete heterogeneous multiprocessor design at different levels of abstraction. “OVP Fast Processor Models are an essential foundation to system level design, helping to unleash innovation in this area,” said Enno Wein, founder and CEO of ProximusDA. “By providing free models and associated virtual prototyping infrastructure, OVP enables the ecosystem to focus on advanced technologies and solutions”.
All OVP Fast Processor Models are instruction accurate, and very fast, focused on enabling embedded software developers, especially those building hardware-dependent software such as firmware and bare metal applications, to have a development environment available early to accelerate the software development cycle. OVP Fast Processor Models work with the OVPsim and Imperas simulators, which employ a state of the art just-in-time code morphing engine to achieve the simulation speed. Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP models. The native TLM-2.0 interface enables multiple instantiations of the processor models in a single virtual platform, just as any other component would be instantiated. The OVP simulator can also be encapsulated within the Eclipse IDE, enabling easy use for software developers.
“SoC development – system, hardware, software – has become an incredibly complex project,” said Simon Davidmann, president and CEO, Imperas. “One company cannot hope to address all the needs, especially as those needs are constantly evolving. By providing significant technology as Open Virtual Platforms, and creating a collaborative environment for tool vendors, IP developers, users and academics, we are contributing to the evolution of a new SoC and embedded system design methodology.”
Aldec, Cadence and Proximus will all have demos showing the integrations available for users to watch at the upcoming Design Automation Conference (DAC) in San Diego. Imperas can also be seen at DAC presenting at the North American SystemC User Group (NASCUG) on Monday June 6, and participating in a pavilion panel session on embedded operating systems on Tuesday June 7.
About Imperas (www.Imperas.com)
For more information about Imperas, please go to the Imperas website.
About the Open Virtual Platforms Initiative (www.OVPworld.org)
For more information about OVP, please go to the About OVP page on the OVP website.