48th Design Automation Conference – San Diego, California, June 6, 2011. Today Imec and Target Compiler Technologies present a C-programmable flexible FEC (forward error correction) solution fit for future cellular, connectivity and broadcasting standards. This so-called “flex FEC” solution competes in area and throughput with dedicated fixed-function hardwired implementations, yet offers the flexibility to support multiple standards thanks to software programmability. The C-programmable flex FEC ASIP (application-specific instruction-set processor) template supports LDPC (low-density parity check), Turbo and Viterbi decoding. Imec designed and optimized the ASIP architecture and generated a matching software development kit, using IP Designer, Target’s tool-suite for ASIP design.
Liesbet Van der Perre, Green Radio Program Director at imec said: “To support the industry’s search for increased flexibility and reliability for their next-generation wireless devices, imec’s green radio program aims at developing solutions for low-cost and low-power reconfigurable radios. Multistandard flex FEC decoders will become ever more important as enablers for future 4G networks. Therefore, we are pleased that Target’s IP Designer tool-suite enabled the design of our flexible C-programmable FEC processor template, offering competitive area and throughput numbers compared to dedicated fixed-function hardwired implementations, while offering full hardware reuse and flexible memory allocation.”
Imec’s ASIP architecture template can be instantiated for different standards to perform channel decoding. Various algorithmic-architectural co-optimizations enabled parallelization of the algorithms to meet the high throughput and latency requirements in a flexible processor. The solution meets throughput and latency specifications ranging from connectivity (WLAN 802.11n, 802.11ac) to broadcasting (DVB-T2/S2, CMMB, DVB-SH) and cellular standards (3GPP-LTE, 802.16e).
Target Compiler Technologies’ IP Designer tool-suite enabled the design-time architectural exploration and optimization of imec’s flex FEC solution and allowed a quick validation of the impact of architectural changes on throughput, latency, silicon area and power consumption. IP Designer automatically generated an optimizing C-compiler to compile the multi-standard FEC algorithms on the specialized FEC architecture exploiting the available instruction-level parallelism, and an instruction-set simulator to validate and profile the code running on the architecture.
The flex FEC template was instantiated for WLAN, WiMAX, 3GPP-LTE and DVB-S2/T2. A low-power register-transfer level hardware implementation of the core was automatically generated with the IP Designer tools, which resulted in a total core area and throughput competitive with state-of-the-art dedicated fixed-function hardwired solutions. The generic template, supporting both turbo and LDPC decoding can be pruned aggressively in case of LDPC decoding only, leading to substantial additional savings in area and power consumption (see table below).
Table: Throughput (Mbps/iteration) on different implementations of a single flex FEC core
|Algorithm ||Mode ||Throughput (output rate)|
|Generic instance (800MHz clock frequency, 1.17sqmm, TSMC 40nm G)|
|Viterbi ||802.11n- 64 bits ||330.3|
| ||802.11n - 1,024 bits ||696.6|
|LDPC ||802.11n - Z=81 - CR 5/6 ||3,590.0|
| ||802.16e - Z=96 - CR 5/6 ||4,208.2|
|Turbo ||3GPP - 6,144 bits - CR 1/3 ||541.1|
|LDPC specific instance (600MHz clock frequency, 1.97sqmmTSMC 40nm G)|
|LDPC ||802.11n - Z=81 CR 5/6 ||3,365.6|
| ||DVB-S2/T2 - Z=360 - CR 5/6 ||9,818.2|
Gert Goossens, Target’s CEO, said: “We are delighted with the ASIP implementation achievements of imec’s green radio program based on our IP Designer tools. This flex FEC template proves that programmable ASIP solutions can compete with fixed-function hardwired IP blocks in performance and area, for advanced wireless standards. In general, ASIP implementations reduce the design risk, can resolve issues with early non-frozen standards and enable SoC customers to include proprietary features in their chipsets. In recent years, IP Designer has been adopted by major industrial players to design their wireless modem solutions. Imec’s new flex FEC solution underscores the potential of ASIPs and of our tools also for next-generation wireless systems.”
Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China and Japan. Its staff of about 1,900 people includes over 550 industrial residents and guest researchers. In 2010, imec's revenue (P&L) was 285 million euro. Further information on imec can be found at www.imec.be.
About Target Compiler Technologies
Target Compiler Technologies (www.retarget.com) is the leading provider of retargetable software tools to accelerate the design, programming and verification of application-specific processor cores (ASIPs). Target's IP Designer tool suite is ideally suited for SoC designs in markets that mandate low silicon cost, low energy consumption, and flexibility to accommodate algorithmic changes. The tools have been used by customers around the globe to design SoCs for 2G/3G/4G handsets, cordless and VoIP phones, audio/video/image processing, infotainment and security for cars, DSL modems, DSL access multiplexers, wireless LAN, hearing instruments, and personal healthcare systems. Target is a spin-off of the Belgian nano-electronics R&D center IMEC, is headquartered in Leuven, Belgium, with North American operations in Boulder, Colorado.