Eliminates Costly VCXOs and VCXOs
IMS2011 Baltimore, MD - June 7, 2011 - Kaben Wireless Silicon Inc. ("Kaben") a recognized industry leader in low-jitter, low-phase noise synthesizers and advanced on-chip filter technology, announced today the pre-release of the KWS430 Jitter Attenuator (JAT), the world's first Programmable JAT IP block for SoC integration.
Data streams in telecom and datacom applications can contain significant amounts of jitter as seen at the far end of an interface link. Since components of a recovered clock's jitter cannot be equalized out, alternative methods are required to clean the clock necessary for low BER and link integrity. Jitter Attenuators apply the jittered clock into the reference pin of a PLL, having very low bandwidth, to attenuate the incoming jitter. However, such systems utilize costly VCXOs or VCSOs to reduce intrinsic noise. The KWS430 eliminates the VCXOs/VCSOs by replacing them with an inexpensive crystal.
The KWS430 JAT performs clock cleaning on a jittered clock up to 1330MHz, and is unique in that it can derive the clean clock from accepting NRZ data inputs directly, at data rates up to 1.33Gb/s.
"The addition of this high performance Programmable JAT complements Kaben's benchmark synthesizer and timing product portfolio very nicely, commented Bill Bereza, Kaben's Director of Marketing. The JAT will produce a clock output with as little as 0.35ps RMS jitter from a 12kHz to 20MHz integration bandwidth ideal for telecom, datacom and server applications. Our JAT replaces several off-chip components including VCXOs and VCSOs typically used today", he went on to say.
The KWS430 output frequency is programmable from 10MHz to 1GHz in steps of 10Hz and delivers 0.35ps RMS jitter in a 12kHz to 20MHz integration bandwidth. The device operates from a 25MHz to 40MHz clock or XTAL reference frequency. The Auto Calibration feature prevents band changes over voltage and temperature. Programming is available through a I2C or SPI interface. The JAT mode can be bypassed and used as a low-jitter NCO, digitally controlled with 22 bits of resolution making it ideal for network synchronization-based SoCs that use digital control loop technologies.
This IP circuit is ideal for SerDes, Optical, Wireless, Wireline and Backhaul applications. The IP is available for integration into a client's ASIC or as a standalone component. The JAT is originally designed in IBM7WL 180nm SiGe BiCMOS and can be ported to any popular process.
About Kaben Wireless, Inc.
Kaben Wireless Silicon Inc is a semiconductor development organization for wireless and wireline communications systems addressing next generation communication standards. We develop circuits and systems for frequency generation and timing products, integrated reconfigurable tuners for software-defined radio, programmable on-chip filters, RF/Analog front ends and systems for proprietary and standards-based applications. Kaben delivers high-performance designs to manufacturers in the wireless and wireline communications market, that significantly reduce risk, cost, and time to market. For more information, please visit www.kabenwireless.com.