HENGELO, - June 8, 2011 – The CRISP consortium, consisting of Recore Systems (project leader), University of Twente, Atmel, Thales, Tampere University of Technology, and NXP Semiconductors, today presents the final demonstrators of the performant General Stream Processor chip. The term General Stream Processor truly applies to this chip, since it works equally well for simple streaming tasks such as position determination for Global Satellite Navigation (using 5 Recore-developed Xentium® DSP cores) as well as for complex tasks such as digital beamforming for radar processing (using over 120 cores simultaneously). Incidentally, the GSP chip is also a programmer’s dream come true: the on-chip ‘run-time resource manager’ assigns tasks to resources during chip operation, and solves the multi-core programmer’s nightmare of figuring out optimal use of resources on beforehand.
Programming many-core systems is known to be difficult. When adding more processing cores that can perform DSP operations in parallel to make a faster system, cores that are waiting for each other may completely reduce the efficiency. The task of the multi-core programmer is to sensibly divide the main task in subtasks and optimally divide them over the available cores (resources). This is a complex problem to solve, even if the main task is fixed, and becomes almost impossible if the tasks change over time or if the number of resources varies over time. To make a programmer’s life more pleasant, the consortium transferred the abstract optimization problem to an on-chip run-time resource manager. “Streaming applications usually involve real-time requirements. To guarantee these, application engineers traditionally need to make very conservative estimates on resource usage and do not tolerate changes to the platform or to neighboring applications” says Timon ter Braak, University of Twente. He continues “The right combination of reconfigurable hardware and run-time resource management can significantly improve the utilization of resources, in particular in the face of changes like for example a failing core”. The resulting programmer-friendly, self-repairing CRISP chip is a big step towards facilitating the adoption of multi-core systems.
Another challenge of multi-cores is how many cores can actually be used at the same time without the system suffering from memory access bottlenecks, a prohibitive amount of cache coherency overhead, or other forms of ‘on-chip traffic jams’ when instructions and computation results travel back and forth from core to memory and core to core. The CRISP consortium implemented solutions based on techniques of distributed memory (memory tiles close to the DSP cores), distributed control, a scalable Network-on-Chip and the use of Xentium DSP cores - IP blocks optimized for use in low-power embedded streaming applications and with far less overhead than a ‘standard’ DSP core. “With the right architectural choices, reconfigurable many-cores can provide the predictability and flexibility needed to support run-time resource management.” says Paul Heysters, Recore Systems. The CRISP consortium implemented the theoretical solutions for solving scalability issues using 3 PCB boards with General Stream Processor chips, resulting in a 138-core system. The run-time resource manager mapped a complex radar application on the system, to process 48 receive channels and compute 24 output beams on 117 cores simultaneously. Paul Heysters of project leader Recore Systems: “We could daisy-chain even more PCB boards to make a 1,000-core, and end up with an expensive gadget just to prove that we can do it. We’re waiting for a sensible real-life application which will challenge us to go beyond the ground-breaking results we’ve already achieved in creating a universal multi-core General Stream Processor.”
The CRISP (Cutting edge Reconfigurable ICs for Stream Processing) project researches optimal utilization, efficient programming and dependability of reconfigurable many-cores for streaming applications. Its goal is to develop a single, highly scalable, reconfigurable system concept that can be used for a wide range of streaming applications; from low-cost consumer applications to very demanding specialty applications. The project consortium consists of Recore Systems (project leader), University of Twente, Atmel Automotive, Thales Netherlands, Tampere University of Technology, and NXP Semiconductors. The project is co-funded by the European Union under the Seventh Framework Programme (FP7).