User View: Low Power Challenges at 40nm and Below

Low power design is hard enough at 65nm and above, and it poses additional challenges at 40nm and below, according to Alex Kuo, department manager at SoC design firm Global Unichip Corp. As noted in another Cadence Community blog post by Qi Wang, Kuo offered a presentation on low-power design at the Cadence booth at the Design Automation Conference (DAC). Separately, I interviewed Kuo at DAC, and what follows are excerpts from a conversation that included such topics as IP integration, power estimation, power network design, dynamic voltage and frequency scaling, and the use of the Common Power Format (CPF).

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