Lowest latency protocol for fault tolerant, mission critical multi-processor systems
Austin, TX - July 18, 2011 - The RapidIO Trade Association announced today a technology roadmap of enhancements with the Serial RapidIO 10xN set of specifications, that moves the protocol to serial lane speed of 10 Gbps and higher supporting individual port speeds that scale beyond 100 Gbps. RapidIO is the embedded interconnect designed for chip to chip, board to board across backplanes, and chassis-to-chassis interconnect of multi processor systems, with ultra low latency, protocol termination in hardware while providing hardware enabled features for fault tolerant mission critical systems. The new technology roadmap scales the needs of RapidIO customers in the wireless, defense, aerospace, imaging, video and server markets beyond what is implementable in other interconnect protocols and sets the stage for OEMs to develop systems with scalable backplanes.
The RapidIO 10xN specification is in development now and is backward compatible with the RapidIO Gen1 and Gen2 systems that are being deployed in the market today. Initially, the RapidIO 10xN specification will support greater than 10 Gbaud per serial lane with lane widths up to x16, resulting in data rates up to 160 Gbps per port. The RapidIO 10xN set of specifications will also scale to serial lane speeds of 25 Gbps and beyond as there are no limitations in the logical and transport layer, thus allowing for the standard to keep in lock step with main stream PHY technology. As key to supporting applications, there is a short-reach specification for local interconnect up to 20 cm over two connectors on FR4 and a long-reach specification that will support up to 1m over two connectors on FR4. Protocol efficiency is further improved by the use of industry leading coding scheme that moves from the 25% overhead of 8b/10b encoding to schemes that have less than 5% encoding overhead. The details of which will be released with specification public release.
"The launch of the new roadmap for RapidIO with the RapidIO 10xN set of specifications is in response to OEMs' significant needs for the capabilities of RapidIO to scale past 6.25 Gbaud per serial lane," said Tom Cox, Executive Director of the RapidIO Trade Association. "The proliferation of 4G handsets is increasingly putting demand on the wireless network, and OEMs need more distributed coverage in smaller form factors, with more data passing between processing elements all with low power and ultra low latency. Cloud computing demands a scalable, energy efficiency fabric within the data centre, and creating scalable systems with 100 Gbps connections to computing nodes, with ultra low latency to enable high volume financial transactions is key. High volume financial systems gain a competitive edge through having the lowest and most deterministic latency. Our defense and aerospace customers continue to rely on RapidIO for mission-critical systems and increased automation of unmanned vehicles. Other operational equipment is driving the need for RapidIO in these demanding real-time processing applications. RapidIO 10xN, with a path to 25xN, sets a long term roadmap to satisfy the real-world needs of all these applications."
The RapidIO 10xN standard defines a superior solution compared to what is available from other protocols. As RapidIO comes directly from the embedded industry, it does not suffer the software overhead, high latency and high processor power consumption necessary when scaling other protocols to 10 Gbps per lane and beyond. With the RapidIO technology roadmap, RapidIO will continue supporting its existing customer base and will also enable the penetration of RapidIO into new markets like server and cloud computing.
Full release of the RapidIO 10xN specification is planned for later in 2011. It is being developed with broad support from all key RapidIO semiconductor, tool and system vendors and builds on widespread traction of RapidIO in Wireless, Defense, Aerospace, Imaging, Video and Cloud Computing markets. For more information or to directly participate in the development of the RapidIO 10xN standard, contact info@RapidIO.org.
The RapidIO Trade Association has a technology roadmap that provides details about RapidIO Specification Gen 2, and previews the development of Specification 10xN and 25xN, which will continue to be defined collaboratively over the next months. While the standard (Specification Rev. 1.3) will continue to dominate embedded applications for the near future, silicon using the 10G is expected to debut in 2012. The embedded systems market has a stable and longer lifecycle then PC and Consumer markets. The needs of this market are reflected in the collaborative efforts of the association's members to develop the appropriate technology, cost and performance in a timeframe suitable for the needs of its members. Details can be found at http://www.rapidio.org/education/Roadmap/
About the RapidIO Standard
The RapidIO standard is the embedded interconnect developed by the embedded market specifically for embedded applications. This ISO-certified, open-standard enables best-in-class quality of service and performance in multi-host embedded processor applications - from components to systems - that require reliable, high speed, cost-effective embedded connectivity. The RapidIO interconnect standard seamlessly enables the chip-to-chip, board-to-board, control, backplane and data plane interconnections needed in high-performance networking, communications and embedded systems.
The RapidIO Trade Association enables, supports and drives the development of the RapidIO ecosystem, and provides the information and resources OEMs need to deliver better solutions, faster. Membership in the RapidIO Trade Association provides the inside track on information, the opportunity to shape specifications, access to pooled resources, and superior overall market awareness. Detailed information on the RapidIO specification, products, design tools, member companies, and membership is available at www.RapidIO.org.