A US-based startup has taken technology developed at the University of Aachen that can be used to build custom embedded processors automatically from a high-level description.
The software produced by Lisatek could threaten the businesses of configurable processor specialists such as ARC International and Tensilica because the tool can be used to customise existing processors as well as create new ones after exploring various architectural alternatives.
Similar to the thrust taken by ARC and Tensilica, and more recently by MIPS Technologies (EETimes, 25/2/02), Lisatek is aiming at the space where hardwired logic is being displaced in favour of high-speed specialised processors.
Uri Mayer, CEO and vice-president of sales, said: "Memories and embedded processors will dominate SoCs. I think that in time, SoC designers will try to design with processors rather than gates, but that is further down the street."
For the moment, the co mpany is aiming at processor designers wanting to model and customise existing processors for specific applications.
The core language behind the toolset, Lisa, is similar to C++ but with extensions for bit-and cycle-accurate modelling. It was devised by Andrean Hoffman, Professor Heinrich Meyr and Stephan Pees of the Integrated Signal Processing Systems laboratory of the University of Aachen in Germany.
Meyr is on the advisory team to Lisatek along with compiler specialist Professor Rainer Leupers, also from the University of Aachen.
The ISS group at Aachen was responsible for the Cossap high-level digital signal processing tool that was spun out to Cadis and then sold to Synopsys in 1994.STMicroelectronics has become the latest company to use the environment for a project based around the ST220 very long instruction word processor.
Mayer said: "They ran a lot of tests with the ST220. For them architectural exploration is a big win. ST already has a project to take what they have today and extend it."
The group used a model built in four weeks using the Lisa language to help develop compilers and suggest architectural changes to the core design team.
Several companies have used the base language on which Lisatek's technology is based already.
Fujitsu signed a deal with the University of Aachen in 2000 to use LISA to model its processors. US-based Morphics and handset maker Nokia have also used the language for modelling and Mayer says Morphics has taped out a design using a processor built with the LISA tools.
There are several components to Lisatek's environment but they are designed to reduce the gap between hardware and software models by using a common specification language, which is Lisa. The language can model processor concepts such as out-of-order execution and VLIW architectures.
"The language is owned by the university but it will be put into the public domain," said Mayer.
The intention is to generate both the implementation and the tool s needed to program the resulting core from the one environment.
Mayer said the processors do not have to be the extensive, general-purpose designs that most developers have become used to programming for.
"We can analyse and create a processor with 10 or 15 instructions if that is all that is needed. Maybe a processor like theTensilica [Xtensa] is overkill," said Mayer.
For the moment, the tool creates a behavioural model and an instruction set simulator as well as assembly-level tools.
"It is not released now but we will be able to go to RTL," said Mayer. RTL generation is likely to be ready by the end of the year. It is currently in beta.
For analysing how the target architecture will run software, the company has built an instruction set simulator. This allows the design to be coupled to a hardware-software simulation using a tool such as Mentor Graphics' Seamless.
The simulator can also be used to debug applications and uses a design modelled on cache-memory c oncepts to speed up operation without losing the ability to stop and analyse the processor's contents.
It works by loading and compiling complete instruction streams, similar to the way that a cache loads a line of memory at once. But, for debugging purposes, the instruction sequence can be broken down to allow debugging techniques such as single-stepping.
One issue that all configurable processor suppliers have had to face is that of building high-level tools such as C compilers for custom architectures. The company has worked with Dutch compiler specialist ACE to take representations built by the Lisatek tools and use them to drive ACE's Cosy tools to automatically generate basic compilers.
"The C compiler issue is a big debate. We can give the capability to run something but maybe it is not optimal. Many people believe that they can do optimised compilers by themselves," said Mayer.
"We have a lot of interfaces. They can take whatever compiler they feel is optimal."
Mayer said the intention is not to compete directly with the configurable processors suppliers. Instead, they may choose to license the Lisatek tools. Processors created using the tools will not incur royalties
"We are using an EDA business model," said Mayer.
Although the pricing is not yet fixed, he said the complete suite of analysis and generation components is likely to cost around $200 000 per seat.